Mohit Bawa d7ef56dbfa drm/amd/display: refactor DSC cap calculation for dcn35
why:
dcn35 currently uses a hardcoded DSC display clock value which is incorrect
for some asic types. Newer DCN versions retrieve dsc display clock from
clk_mgr. The same can be done for dcn35.

how:
Refactor the DSC cap calculation using pre-existing logic.
Handle ODM combine requirements in dc_dsc.c.
Replace hardcoded display clock with actual value retrieved from clk_mgr.

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Mohit Bawa <Mohit.Bawa@amd.com>
Signed-off-by: Fangzhi Zuo <jerry.zuo@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-11-11 21:54:15 -05:00
2025-10-17 13:02:22 +02:00
2025-10-24 14:45:08 +02:00
2025-10-19 15:19:16 -10:00

Linux kernel
============

There are several guides for kernel developers and users. These guides can
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In order to build the documentation, use ``make htmldocs`` or
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Please read the Documentation/process/changes.rst file, as it contains the
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