Zhong Kaihua d33fb1b9f0 clk: hi3660: fix incorrect uart3 clock freqency
UART3 clock rate is doubled in previous commit.

This error is not detected until recently a mezzanine board which makes
real use of uart3 port (through LS connector of 96boards) was setup
and tested on hi3660-hikey960 board.

This patch changes clock source rate of clk_factor_uart3 to 100000000.

Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2017-11-14 09:48:59 -08:00
2017-09-16 15:47:51 -07:00

Linux kernel
============

This file was moved to Documentation/admin-guide/README.rst

Please notice that there are several guides for kernel developers and users.
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Please read the Documentation/process/changes.rst file, as it contains the
requirements for building and running the kernel, and information about
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