Nicholas Susanto cc4d6ea0f2 drm/amd/display: Fix DML2 logic to set clk state to min
[Why]

When an eDP with high clock states is going into s0i3, stream_count is
0. This causes DML to not update the clks to the lowest state and
blocking us to enter s0i3 since eDP is out of vmin.

[How]

When stream_count is 0, set all the clocks to the lowest state.

Reviewed-by: Jun Lei <jun.lei@amd.com>
Acked-by: Zaeem Mohamed <zaeem.mohamed@amd.com>
Signed-off-by: Nicholas Susanto <nicholas.susanto@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-06-05 11:06:12 -04:00
2022-09-28 09:02:20 +02:00
2024-04-21 12:35:54 -07:00
2024-03-18 03:36:32 -06:00

Linux kernel
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