Deepti Jaggi 0edda639ba
mailbox: qcom-cpucp: Add support for Nord CPUCP mailbox controller ...
The Nord SoC CPUCP mailbox supports 16 IPC channels, compared to 3 on
x1e80100. The existing driver hardcodes the channel count via a
compile-time constant (APSS_CPUCP_IPC_CHAN_SUPPORTED), making it
impossible to support hardware with a different number of channels.
Introduce a qcom_cpucp_mbox_data per-hardware configuration struct that
carries the channel count, and retrieve it via of_device_get_match_data()
at probe time. Switch the channel array from a fixed-size member to a
dynamically allocated buffer sized from the hardware data. Update the
x1e80100 entry to supply its own data struct, and add a new Nord entry
with num_chans = 16.
Signed-off-by: Deepti Jaggi <deepti.jaggi@oss.qualcomm.com >
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com >
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com >
Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com >
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