Danijel Slivka afbf7955ff drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts ...

Why:
Setting IH_RB_WPTR register to 0 will not clear the RB_OVERFLOW bit
if RB_ENABLE is not set.

How to fix:
Set WPTR_OVERFLOW_CLEAR bit after RB_ENABLE bit is set.
The RB_ENABLE bit is required to be set, together with
WPTR_OVERFLOW_ENABLE bit so that setting WPTR_OVERFLOW_CLEAR bit
would clear the RB_OVERFLOW.

Signed-off-by: Danijel Slivka <danijel.slivka@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2024-06-27 17:30:27 -04:00

..

drm

drm/amdgpu: clear RB_OVERFLOW bit when enabling interrupts

2024-06-27 17:30:27 -04:00

host1x

Merge tag 'v6.10-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6

2024-05-13 14:53:05 -07:00

ipu-v3

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trace

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vga

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Makefile

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