Ville Syrjälä a43d928120 drm/i915/dsi: Gate DSI clocks earlier ...

The clock gating step is in the wrong spot compared to the
TGL+ bspec sequence. Move it the right place. Windows also
seems to use the TGL+ order here always.

Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230608203057.23759-6-ville.syrjala@linux.intel.com

2023-06-13 19:04:25 +03:00

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drm

drm/i915/dsi: Gate DSI clocks earlier

2023-06-13 19:04:25 +03:00

host1x

Merge tag 'drm/tegra/for-6.4-rc1' of https://gitlab.freedesktop.org/drm/tegra into drm-next

2023-04-06 15:02:17 +02:00

ipu-v3

ipu-v3: Include <linux/io.h>

2023-05-18 11:06:18 +02:00

trace

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vga

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Makefile

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