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Commitb1b90514ea("spi: spi-cadence: Add support for Slave mode") updated the code to trigger the IRQ when the FIFO was half empty, overlapping filling more data into the FIFO and sending what is left. This appears to cause regressions on the Zynq 7000, for transactions longer than the FIFO size, below that no overlapping occurs. It would appear from my testing that any attempt to put new data into the FIFO whilst data is still transmitting causes data corruption on both send and receive. If I am reading the commit message right on commit49530e6411("spi: cadence: Add usleep_range() for cdns_spi_fill_tx_fifo()"), that would also seem to imply this is the case. On the assumption that this isn't an issue on the platform the original slave mode support was added for, update the cdns_transfer_one to only set the watermark to 50% of the FIFO size when in slave mode. There by retaining the new behaviour for slave mode but reverting to the older behaviour when the SPI is used a master. Fixes:b1b90514ea("spi: spi-cadence: Add support for Slave mode") Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com Link: https://lore.kernel.org/r/20230509164153.3907694-2-ckeepax@opensource.cirrus.com Signed-off-by: Mark Brown <broonie@kernel.org
Linux kernel
============
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