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Ciprian Regus says: ==================== net: Add ADIN1140 support This series introduces support for the ADIN1140 (also called AD3306) 10BASE-T1S single port MACPHY. The device integrates the MAC and PHY in the same package. The communication with the host CPU is done through an SPI interface, using the Open Alliance TC6 protocol for control and data transactions. As a result, the oa_tc6 framework is used to implement the communication with the device (register accesses and Ethernet frame RX/TX). The MAC and PHY are connected internally using an MII and MDIO bus. The PHY is a half duplex 10Mbps device, which implements both the PLCA RS (IEEE 802.3 clause 148) and CSMA/CD methods of accessing the Ethernet medium. The 10BASE-T1S standard allows multiple PHY devices to be connected (in parallel) on the same single twisted pair network segment, so PLCA can be configured in order to provide a fair access scheme to all the nodes and reduce the jitter introduced by the unordered CSMA/CD transmits. The PHY's internal register map can be accessed using the direct MDIO mode of the OA TC6. The control, status, phy id 1 & 2 C22 registers are mapped to the 0xFF00 - 0xFF03 range. As for C45 addressable devices, the PHY has PCS, PMA and PLCA blocks. The oa_tc6 framework patches are changes that would make the library usable by the subsequent ADIN1140 MAC driver. The protected mode patch is required because the ADIN1140 only allows protected mode OA TC6 control transactions, which the oa_tc6 framework doesn't currently implement. The OA_TC6_BROKEN_PHY quirk patch is required in order to allow the MAC driver to have a custom implementation for the mii_bus access methods as a workaround for hardware issues: 1. The OA TC6 standard defines the direct and indirect access modes for MDIO transactions. The ADIN1140 incorrectly advertises indirect mode only (supported capabilities register - 0x2, bit 9), while actually implementing just the direct mode. We cannot rely on the CAP register to choose an access method (which oa_tc6 does by default, even though it only implements the direct mode), so the driver has to use its own. 2. The ADIN1140 cannot access the C22 register space of the internal PHY, while the PHY is busy receiving frames. If that happens, the CONFIG0 and CONFIG2 registers of the MAC will get corrupted and the data transfer will stop. Those two registers configure settings for the transfer protocol between the MAC and host, so the value for some of their subfields shouldn't be changed while the netdev is up. Since we know the PHY is internal, the MAC driver can implement a custom mii_bus, which can intercept C22 accesses. Most of the registers mapped in the 0x0 - 0x3 range (the only ones the PHY offers) are read only, and their value can be read from somewhere else (e.g the PHYID 1 & 2 have the same value as 0x1 in the MAC memory map). C45 accesses do not cause this issue, so we can properly implement them. Even though they have different driver, the MAC one cannot function without the PHY driver, since the PHY is not compatible with the generic c22 driver. As such CONFIG_ADIN1140 selects CONFIG_ADIN1140_PHY. Signed-off-by: Ciprian Regus <ciprian.regus@analog.com> ==================== Link: https://patch.msgid.link/20260708-adin1140-driver-v5-0-4aca7b51a58b@analog.com Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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