Current FastRPC context uses a 12-bit mask:
[ID(8 bits)][PD type(4 bits)] = GENMASK(11, 4)
This works for normal calls but fails for DSP polling mode.
Polling mode expects a 16-bit layout:
[15:8] = context ID (8 bits)
[7:5] = reserved
[4] = async mode bit
[3:0] = PD type (4 bits)
If async bit (bit 4) is set, DSP disables polling. With current
mask, odd IDs can set this bit, causing DSP to skip poll updates.
Update FASTRPC_CTXID_MASK to GENMASK(15, 8) so IDs occupy upper
byte and lower byte is left for DSP flags and PD type.
Reserved bits remain unused. This change is compatible with
polling mode and does not break non-polling behavior.
Bit layout:
[15:8] = CCCCCCCC (context ID)
[7:5] = xxx (reserved)
[4] = A (async mode)
[3:0] = PPPP (PD type)
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Ekansh Gupta <ekansh.gupta@oss.qualcomm.com>
Signed-off-by: Srinivas Kandagatla <srini@kernel.org>
Link: https://patch.msgid.link/20260729094352.111065-7-srini@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
62373b7879