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Merge tag 'reset-fixes-for-v7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/pza/linux into arm/fixes
Reset controller fixes for v7.2
* Fix the SpacemiT K3 USB2 AHB reset bit location.
* Add missing COMBOPHY_RESET definition for Altera Agilex5.
* Fix the reset-sunxi initialization error path to release the
requested memory region.
* Correct polarity of MIPI CSI resets on NXP i.MX8MQ. The corresponding
fix in the CSI2 driver, 6d79bb8fd2, is already contained in v7.2-rc1.
* tag 'reset-fixes-for-v7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/pza/linux:
reset: imx7: Correct polarity of MIPI CSI resets on i.MX8MQ
reset: sunxi: fix memory region leak on ioremap failure
dt-bindings: reset: altr: add COMBOPHY_RESET for Agilex5
reset: spacemit: k3: fix USB2 ahb reset
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
@@ -236,6 +236,12 @@ static int imx8mq_reset_set(struct reset_controller_dev *rcdev,
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case IMX8MQ_RESET_PCIE_CTRL_APPS_EN:
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case IMX8MQ_RESET_PCIE2_CTRL_APPS_EN:
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case IMX8MQ_RESET_MIPI_CSI1_CORE_RESET:
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case IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET:
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case IMX8MQ_RESET_MIPI_CSI1_ESC_RESET:
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case IMX8MQ_RESET_MIPI_CSI2_CORE_RESET:
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case IMX8MQ_RESET_MIPI_CSI2_PHY_REF_RESET:
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case IMX8MQ_RESET_MIPI_CSI2_ESC_RESET:
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case IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N:
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case IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N:
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case IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N:
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@@ -44,7 +44,7 @@ static int sunxi_reset_init(struct device_node *np)
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data->membase = ioremap(res.start, size);
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if (!data->membase) {
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ret = -ENOMEM;
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goto err_alloc;
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goto err_mem_region;
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}
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spin_lock_init(&data->lock);
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@@ -57,6 +57,8 @@ static int sunxi_reset_init(struct device_node *np)
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return reset_controller_register(&data->rcdev);
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err_mem_region:
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release_mem_region(res.start, size);
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err_alloc:
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kfree(data);
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return ret;
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@@ -112,7 +112,7 @@ static const struct ccu_reset_data k3_apmu_resets[] = {
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[RESET_APMU_SDH0] = RESET_DATA(APMU_SDH0_CLK_RES_CTRL, 0, BIT(1)),
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[RESET_APMU_SDH1] = RESET_DATA(APMU_SDH1_CLK_RES_CTRL, 0, BIT(1)),
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[RESET_APMU_SDH2] = RESET_DATA(APMU_SDH2_CLK_RES_CTRL, 0, BIT(1)),
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[RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(1)),
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[RESET_APMU_USB2_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(0)),
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[RESET_APMU_USB2_VCC] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(2)),
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[RESET_APMU_USB2_PHY] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(3)),
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[RESET_APMU_USB3_A_AHB] = RESET_DATA(APMU_USB_CLK_RES_CTRL, 0, BIT(5)),
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@@ -22,7 +22,7 @@
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#define USB0_RESET 35
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#define USB1_RESET 36
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#define NAND_RESET 37
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/* 38 is empty */
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#define COMBOPHY_RESET 38
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#define SDMMC_RESET 39
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#define EMAC0_OCP_RESET 40
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#define EMAC1_OCP_RESET 41
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