Daniel Vetter 5d536e2858 drm/i915: dvo needs a P2 divisor of 4 ...

Section 1.5.4, "DPLL A Control Register" from Bspec about bit 23
"FPA0/A1 P2 Clock Divide":

0 = Divide by 2
1 = Divide by 4. This bit must be set in DVO non-gang mode

So copy the current limits (which should be good for i8xx) and create
a new set for dvo encoders.

Reviewed-by: Chris Wilson <chris@chris-wilson.oc.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

2013-07-08 22:04:38 +02:00

..

drm

drm/i915: dvo needs a P2 divisor of 4

2013-07-08 22:04:38 +02:00

host1x

gpu: host1x: Rework CPU syncpoint increment

2013-06-22 12:43:55 +02:00

vga

fbcon: fix locking harder

2013-02-08 12:02:43 +10:00

Makefile

gpu: host1x: Add host1x driver

2013-04-22 12:32:40 +02:00