Files
linux/drivers
Sakari Ailus 482e75e7b3 media: ccs-pll: Avoid overflow in pre-PLL divisor lower bound search
The external clock frequency times the PLL multiplier may exceed the value
range of 32-bit unsigned integers. Instead perform the same calculation y
using two divisions.

The result has some potential to be different, but that's ok: this number
is used to limit the range of pre-PLL divisors to find optimal values. So
the effect of the rare case of a different result here would mean an
invalid pre-PLL divisor is tried. That will be found out a little later in
any case.

Also guard against dividing by zero if the external clock frequency is
higher than the maximum OP PLL output clock --- a rather improbable case.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
2020-12-07 15:49:32 +01:00
..
2020-11-18 16:42:07 -08:00
2020-11-12 13:59:04 -07:00
2020-11-11 09:53:09 +01:00
2020-09-28 12:17:36 +02:00
2020-09-25 06:12:15 +02:00
2020-10-27 19:23:04 +01:00