Claudiu Beznea 35d06f7478 clk: at91: sam9x60-pll: use frac when setting frequency
In commit a436c2a447 ("clk: at91: add sam9x60 PLL driver")
the fractional part of PLL wasn't set on registers but it was
calculated and taken into account for determining div and mul
(see sam9x60_pll_get_best_div_mul()).

Fixes: a436c2a447 ("clk: at91: add sam9x60 PLL driver")
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1595403506-8209-7-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-07-24 02:18:47 -07:00
2020-06-14 12:45:04 -07:00

Linux kernel
============

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