Feifei Xu 2b3a1f515f drm/amdgpu:Add pcie gen5 support in pcie capability. ...

Add PCIE_SPEED_32_0GT and PCIE GEN5 support for amdgpu.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2021-01-21 09:54:56 -05:00

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asic_reg

drm/amdgpu: add osssys v4_2 ip headers (v2)

2020-12-23 15:05:20 -05:00

ivsrcid

drm/amdgpu: add sdma2 and sdma3 irqsrc header files for sienna_cichlid (v2)

2020-06-03 13:52:03 -04:00

amd_acpi.h

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amd_pcie_helpers.h

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amd_pcie.h

drm/amdgpu:Add pcie gen5 support in pcie capability.

2021-01-21 09:54:56 -05:00

amd_shared.h

drm/amdgpu: Add GFX Fine Grain Clock Gating flag

2020-11-04 17:08:08 -05:00

arct_ip_offset.h

drm/amd/include/arct_ip_offset: Mark top-level IP_BASE definition as __maybe_unused

2020-11-24 12:09:53 -05:00

atom-bits.h

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atom-names.h

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atom-types.h

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atombios.h

drm/amd/pm: correct VR shared rail info

2020-10-27 11:58:57 -04:00

atomfirmware.h

drm/amdgpu: new macro for determining 2ND_USB20PORT support

2020-12-10 16:41:49 -05:00

atomfirmwareid.h

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cgs_common.h

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cik_structs.h

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dimgrey_cavefish_ip_offset.h

drm/amd/include/dimgrey_cavefish_ip_offset: Mark top-level IP_BASE as __maybe_unused

2020-11-24 12:09:53 -05:00

discovery.h

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displayobject.h

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dm_pp_interface.h

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kgd_kfd_interface.h

Merge tag 'drm-next-2020-10-15' of git://anongit.freedesktop.org/drm/drm

2020-10-15 10:46:16 -07:00

kgd_pp_interface.h

drm/amd/pm: implement processor fine grain feature for vangogh (v3)

2021-01-13 23:52:58 -05:00

navi10_enum.h

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navi10_ip_offset.h

drm/amd/include/navi10_ip_offset: Mark top-level IP_BASE as __maybe_unused

2020-11-24 12:09:53 -05:00

navi12_ip_offset.h

drm/amd/include/navi12_ip_offset: Mark top-level IP_BASE as __maybe_unused

2020-11-24 12:09:53 -05:00

navi14_ip_offset.h

drm/amd/include/navi14_ip_offset: Mark top-level IP_BASE as __maybe_unused

2020-11-24 12:09:53 -05:00

pptable.h

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renoir_ip_offset.h

drm/amd/include/renoir_ip_offset: Mark top-level IP_BASE as __maybe_unused

2021-01-14 13:20:20 -05:00

sienna_cichlid_ip_offset.h

drm/amd/include/sienna_cichlid_ip_offset: Mark top-level IP_BASE as __maybe_unused

2020-11-24 12:09:53 -05:00

soc15_hw_ip.h

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soc15_ih_clientid.h

drm/amdgpu: correct SDMA3 IH clinet id for sienna_cichlid

2020-06-03 13:52:04 -04:00

v9_structs.h

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v10_structs.h

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vangogh_ip_offset.h

drm/amd/include/vangogh_ip_offset: Mark top-level IP_BASE as __maybe_unused

2020-11-24 12:09:53 -05:00

vega10_enum.h

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vega10_ip_offset.h

drm/amd/include/vega10_ip_offset: Mark _BASE structs as __maybe_unused

2020-11-13 17:29:46 -05:00

vega20_ip_offset.h

drm/amd/include/vega20_ip_offset: Mark top-level IP_BASE definition as __maybe_unused

2020-11-24 12:09:53 -05:00

vi_structs.h

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