Dinh Nguyen 0ffc5df823 ARM: dts: socfpga: update NAND clocking for c5/a5
The NAND IP needs 3 clocks(nand_x_clk, nand_clk, and nand_ecc_clk). The
nand_x_clk and nand_ecc_clk are derived from the nand_clk. The nand_x_clk
has a fixed divider of 4.

Also, update the NAND dts property with the correct clocks property.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
---
v2: add nand_ecc_clk and update commit message
2018-08-30 08:38:26 -05:00
2018-08-26 14:11:59 -07:00

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