Files
linux/drivers/gpu/drm
Philip Yang 0f12a22f37 drm/amdgpu: Flush TLB after mapping for VG20+XGMI
For VG20 + XGMI bridge, all mappings PTEs cache in TC, this may have
stall invalid PTEs in TC because one cache line has 8 pages. Need always
flush_tlb after updating mapping.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-04-05 10:29:47 -04:00
..
2022-02-07 16:35:35 -08:00
2021-08-10 20:14:01 +02:00
2022-03-15 15:01:12 -04:00
2022-02-07 16:35:35 -08:00
2021-08-10 20:14:01 +02:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2022-02-07 16:35:35 -08:00
2021-08-02 10:19:43 +02:00
2021-08-02 10:19:43 +02:00
2021-11-30 09:41:28 +01:00
2021-08-02 10:19:43 +02:00
2021-10-01 15:55:47 +02:00
2021-11-30 09:41:28 +01:00
2022-02-07 16:35:35 -08:00
2021-08-19 09:02:55 +09:00
2021-08-02 10:19:43 +02:00
2021-08-10 20:14:01 +02:00
2021-08-02 10:19:43 +02:00