Philip Yang 0f12a22f37 drm/amdgpu: Flush TLB after mapping for VG20+XGMI ...

For VG20 + XGMI bridge, all mappings PTEs cache in TC, this may have
stall invalid PTEs in TC because one cache line has 8 pages. Need always
flush_tlb after updating mapping.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

2022-04-05 10:29:47 -04:00

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drm

drm/amdgpu: Flush TLB after mapping for VG20+XGMI

2022-04-05 10:29:47 -04:00

host1x

gpu: host1x: Fix a memory leak in 'host1x_remove()'

2022-03-01 11:13:09 +01:00

ipu-v3

media: i.MX6: Support 16-bit BT.1120 video input

2021-10-19 08:08:38 +01:00

trace

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vga

vgaarb: don't pass a cookie to vga_client_register

2021-07-21 10:29:10 +02:00

Makefile

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