Files
linux/drivers/net
Zumeng Chen ffac0e967f net: macb: ensure ordering write to re-enable RX smoothly
When a hardware issue happened as described by inline comments, the register
write pattern looks like the following:

<write ~MACB_BIT(RE)>
+ wmb();
<write MACB_BIT(RE)>

There might be a memory barrier between these two write operations, so add wmb
to ensure an flip from 0 to 1 for NCR.

Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-11-29 20:33:55 -05:00
..
2016-06-15 22:06:06 -07:00
2016-08-15 11:57:55 -07:00
2016-11-27 19:59:50 -05:00
2016-08-31 14:33:09 -07:00
2016-05-09 00:00:28 -04:00
2016-09-20 22:55:23 -04:00
2016-08-30 22:27:18 -07:00
2016-11-09 18:59:50 -05:00