Files
linux/drivers
Zumeng Chen ffac0e967f net: macb: ensure ordering write to re-enable RX smoothly
When a hardware issue happened as described by inline comments, the register
write pattern looks like the following:

<write ~MACB_BIT(RE)>
+ wmb();
<write MACB_BIT(RE)>

There might be a memory barrier between these two write operations, so add wmb
to ensure an flip from 0 to 1 for NCR.

Signed-off-by: Zumeng Chen <zumeng.chen@windriver.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2016-11-29 20:33:55 -05:00
..
2016-11-16 20:46:32 +01:00
2016-09-27 12:33:47 +02:00
2016-11-16 12:39:57 -07:00
2016-11-01 09:04:04 -06:00