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Antoine Tenart says: ==================== net: mvpp2: improve the interrupt usage This series aims to improve the interrupts descriptions and usage in the Marvell PPv2 driver. - Before the series interrupts were named after their s/w usage, which in fact can be configured. The series rename all those interrupts and add a description of the ones left over. - In PPv2 the interrupts are mapped to vectors. Those vectors were directly mapped to a given CPU, and per-cpu accesses were done. While this worked on our cases, the registers accesses mapped to the vectors are not actually linked to a given CPU. They instead are linked to what is called a "s/w thread". The series modify this so that the s/w threads are used instead of the CPU numbers, by adding an indirection. This means we now can have systems with more CPUs than s/w threads. This is based on today's net-next, and was tested on various boards using both versions of the PPv2 engine. Two more patches will be coming, to update the device trees describing a PPv2 engine. The patches are ready, but will go through a different tree. I'll send them once this series will be accepted. This is not an issue as the PPv2 driver keeps the dt bindings backward compatibility. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
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