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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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36a0245666
Use get_smn_base interface to get IP die instance's base offset in aqua_vanjaram. encode_ext_smn_addressing is not used. Signed-off-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
164 lines
6.9 KiB
C
164 lines
6.9 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2025 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __AMDGPU_REG_ACCESS_H__
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#define __AMDGPU_REG_ACCESS_H__
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include "amdgpu_ip.h"
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struct amdgpu_device;
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typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device *, uint32_t);
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typedef void (*amdgpu_wreg_t)(struct amdgpu_device *, uint32_t, uint32_t);
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typedef uint32_t (*amdgpu_rreg_ext_t)(struct amdgpu_device *, uint64_t);
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typedef void (*amdgpu_wreg_ext_t)(struct amdgpu_device *, uint64_t, uint32_t);
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typedef uint64_t (*amdgpu_rreg64_t)(struct amdgpu_device *, uint32_t);
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typedef void (*amdgpu_wreg64_t)(struct amdgpu_device *, uint32_t, uint64_t);
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typedef uint64_t (*amdgpu_rreg64_ext_t)(struct amdgpu_device *, uint64_t);
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typedef void (*amdgpu_wreg64_ext_t)(struct amdgpu_device *, uint64_t, uint64_t);
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typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device *, uint32_t,
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uint32_t);
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typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device *, uint32_t, uint32_t,
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uint32_t);
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typedef uint64_t (*amdgpu_reg_get_smn_base64_t)(struct amdgpu_device *adev,
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enum amd_hw_ip_block_type block,
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int die_inst);
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struct amdgpu_reg_ind {
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spinlock_t lock;
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amdgpu_rreg_t rreg;
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amdgpu_wreg_t wreg;
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};
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struct amdgpu_reg_ind_blk {
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spinlock_t lock;
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amdgpu_block_rreg_t rreg;
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amdgpu_block_wreg_t wreg;
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};
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struct amdgpu_reg_pcie_ind {
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spinlock_t lock;
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amdgpu_rreg_t rreg;
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amdgpu_wreg_t wreg;
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amdgpu_rreg_ext_t rreg_ext;
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amdgpu_wreg_ext_t wreg_ext;
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amdgpu_rreg64_t rreg64;
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amdgpu_wreg64_t wreg64;
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amdgpu_rreg64_ext_t rreg64_ext;
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amdgpu_wreg64_ext_t wreg64_ext;
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amdgpu_rreg_t port_rreg;
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amdgpu_wreg_t port_wreg;
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};
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struct amdgpu_reg_smn_ext {
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amdgpu_reg_get_smn_base64_t get_smn_base;
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};
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struct amdgpu_reg_access {
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struct amdgpu_reg_ind smc;
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struct amdgpu_reg_ind uvd_ctx;
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struct amdgpu_reg_ind didt;
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struct amdgpu_reg_ind gc_cac;
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struct amdgpu_reg_ind se_cac;
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struct amdgpu_reg_ind_blk audio_endpt;
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struct amdgpu_reg_pcie_ind pcie;
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struct amdgpu_reg_smn_ext smn;
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};
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void amdgpu_reg_access_init(struct amdgpu_device *adev);
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uint32_t amdgpu_reg_smc_rd32(struct amdgpu_device *adev, uint32_t reg);
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void amdgpu_reg_smc_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
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uint32_t amdgpu_reg_uvd_ctx_rd32(struct amdgpu_device *adev, uint32_t reg);
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void amdgpu_reg_uvd_ctx_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
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uint32_t amdgpu_reg_didt_rd32(struct amdgpu_device *adev, uint32_t reg);
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void amdgpu_reg_didt_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
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uint32_t amdgpu_reg_gc_cac_rd32(struct amdgpu_device *adev, uint32_t reg);
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void amdgpu_reg_gc_cac_wr32(struct amdgpu_device *adev, uint32_t reg,
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uint32_t v);
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uint32_t amdgpu_reg_se_cac_rd32(struct amdgpu_device *adev, uint32_t reg);
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void amdgpu_reg_se_cac_wr32(struct amdgpu_device *adev, uint32_t reg,
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uint32_t v);
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uint32_t amdgpu_reg_audio_endpt_rd32(struct amdgpu_device *adev, uint32_t block,
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uint32_t reg);
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void amdgpu_reg_audio_endpt_wr32(struct amdgpu_device *adev, uint32_t block,
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uint32_t reg, uint32_t v);
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uint32_t amdgpu_reg_pcie_rd32(struct amdgpu_device *adev, uint32_t reg);
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void amdgpu_reg_pcie_wr32(struct amdgpu_device *adev, uint32_t reg, uint32_t v);
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uint32_t amdgpu_reg_pcie_ext_rd32(struct amdgpu_device *adev, uint64_t reg);
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void amdgpu_reg_pcie_ext_wr32(struct amdgpu_device *adev, uint64_t reg,
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uint32_t v);
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uint64_t amdgpu_reg_pcie_rd64(struct amdgpu_device *adev, uint32_t reg);
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void amdgpu_reg_pcie_wr64(struct amdgpu_device *adev, uint32_t reg, uint64_t v);
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uint64_t amdgpu_reg_pcie_ext_rd64(struct amdgpu_device *adev, uint64_t reg);
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void amdgpu_reg_pcie_ext_wr64(struct amdgpu_device *adev, uint64_t reg,
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uint64_t v);
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uint32_t amdgpu_reg_pciep_rd32(struct amdgpu_device *adev, uint32_t reg);
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void amdgpu_reg_pciep_wr32(struct amdgpu_device *adev, uint32_t reg,
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uint32_t v);
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uint64_t amdgpu_reg_get_smn_base64(struct amdgpu_device *adev,
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enum amd_hw_ip_block_type block,
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int die_inst);
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uint64_t amdgpu_reg_smn_v1_0_get_base(struct amdgpu_device *adev,
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enum amd_hw_ip_block_type block,
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int die_inst);
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uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, uint32_t reg,
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uint32_t acc_flags);
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uint32_t amdgpu_device_xcc_rreg(struct amdgpu_device *adev, uint32_t reg,
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uint32_t acc_flags, uint32_t xcc_id);
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void amdgpu_device_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
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uint32_t acc_flags);
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void amdgpu_device_xcc_wreg(struct amdgpu_device *adev, uint32_t reg,
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uint32_t v, uint32_t acc_flags, uint32_t xcc_id);
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void amdgpu_mm_wreg_mmio_rlc(struct amdgpu_device *adev, uint32_t reg,
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uint32_t v, uint32_t xcc_id);
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void amdgpu_mm_wreg8(struct amdgpu_device *adev, uint32_t offset,
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uint8_t value);
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uint8_t amdgpu_mm_rreg8(struct amdgpu_device *adev, uint32_t offset);
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u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, u32 reg_addr);
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u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, u64 reg_addr);
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u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, u32 reg_addr);
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u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, u64 reg_addr);
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void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, u32 reg_addr,
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u32 reg_data);
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void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, u64 reg_addr,
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u32 reg_data);
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void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, u32 reg_addr,
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u64 reg_data);
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void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, u64 reg_addr,
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u64 reg_data);
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u32 amdgpu_device_pcie_port_rreg(struct amdgpu_device *adev, u32 reg);
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void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
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uint32_t amdgpu_device_wait_on_rreg(struct amdgpu_device *adev, uint32_t inst,
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uint32_t reg_addr, char reg_name[],
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uint32_t expected_value, uint32_t mask);
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#endif /* __AMDGPU_REG_ACCESS_H__ */
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