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2050b57ecd
Add the new Clock manager driver to support new Agilex5 platform. The new driver got rid of the clk_parent_data structures as there are no 'clock-names' property in the DT bindings and use parent_names internally. This is based on the previous feedback from the maintainer. Signed-off-by: Ang Tien Sung <tiensung.ang@altera.com> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
7 lines
311 B
Makefile
7 lines
311 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_CLK_INTEL_SOCFPGA32) += clk.o clk-gate.o clk-pll.o clk-periph.o \
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clk-pll-a10.o clk-periph-a10.o clk-gate-a10.o
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obj-$(CONFIG_CLK_INTEL_SOCFPGA64) += clk-s10.o \
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clk-pll-s10.o clk-periph-s10.o clk-gate-s10.o \
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clk-agilex.o clk-agilex5.o
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