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2050b57ecd
Add the new Clock manager driver to support new Agilex5 platform. The new driver got rid of the clk_parent_data structures as there are no 'clock-names' property in the DT bindings and use parent_names internally. This is based on the previous feedback from the maintainer. Signed-off-by: Ang Tien Sung <tiensung.ang@altera.com> Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
20 lines
716 B
Plaintext
20 lines
716 B
Plaintext
# SPDX-License-Identifier: GPL-2.0
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config CLK_INTEL_SOCFPGA
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bool "Intel SoCFPGA family clock support" if COMPILE_TEST && !ARCH_INTEL_SOCFPGA
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default ARCH_INTEL_SOCFPGA
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help
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Support for the clock controllers present on Intel SoCFPGA and eASIC
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devices like Aria, Cyclone, Stratix 10, Agilex and N5X eASIC.
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if CLK_INTEL_SOCFPGA
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config CLK_INTEL_SOCFPGA32
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bool "Intel Aria / Cyclone clock controller support" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
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default ARM && ARCH_INTEL_SOCFPGA
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config CLK_INTEL_SOCFPGA64
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bool "Intel Stratix / Agilex / N5X / Agilex5 clock controller support" if COMPILE_TEST && (!ARM64 || !ARCH_INTEL_SOCFPGA)
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default ARM64 && ARCH_INTEL_SOCFPGA
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endif # CLK_INTEL_SOCFPGA
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