Nuvoton device tree updates for 5.18
* Additions to wpcm450 following the upstremaing of the pinctrl/gpio
driver for this platform
* Match more of the platform in MAINTAINERS
* tag 'nuvoton-5.18-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc:
MAINTAINERS: ARM/WPCM450: Add 'W:' line with wiki
ARM: dts: wpcm450: Add pinmux information to UART0
ARM: dts: wpcm450-supermicro-x9sci-ln4f: Add GPIO LEDs and buttons
ARM: dts: wpcm450: Add pin functions
ARM: dts: wpcm450: Add pinctrl and GPIO nodes
ARM: dts: wpcm450: Add global control registers (GCR) node
MAINTAINERS: Match all of bindings/arm/npcm/ as part of NPCM architecture
dt-bindings: arm/npcm: Add binding for global control registers (GCR)
Link: https://lore.kernel.org/r/CACPK8XdjF6dG04hR+iMpUP8=LSJi5x-hRivgCGDaY7o_461eJw@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* 'mstar-dt-next' of https://github.com/linux-chenxing/linux:
ARM: mstar: Extend opp_table for infinity2m
ARM: mstar: Add OPP table for infinity3
ARM: mstar: Add OPP table for infinity
ARM: mstar: Link cpupll to second core
ARM: mstar: Link cpupll to cpu
ARM: mstar: Add cpupll to base dtsi
dt-bindings: clk: mstar msc313 cpupll binding description
ARM: dts: mstar: Add board for 100ask DongShanPiOne
dt-bindings: arm: mstar: Add compatible for 100ask DongShanPiOne
dt-bindings: vendor-prefixes: Add prefix for 100ask
ARM: dts: mstar: Add a dts for Miyoo Mini
dt-bindings: arm: mstar: Add compatible for Miyoo Mini
dt-bindings: vendor-prefixes: Add prefix for Miyoo
ARM: dts: mstar: Add the Wireless Tag IDO-SBC2D06-V1B-22W
dt-bindings: add vendor prefix for Wireless Tag
ARM: dts: mstar: Set gpio compatible for ssd20xd
Link: https://lore.kernel.org/r/20220216193131.59794-1-romain.perier@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
IXP4xx patches for the v5.18 kernel cycle:
- Fix up the WG302 to support the v1 version (also tested)
- Fix up the syscon size
- Drop the alias for UART1 in GW7001
* tag 'ixp4xx-dts-v5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: dts: Drop serial 1 alias on GW7001
ARM: dts: ixp42x: Expand syscon register range
ARM: dts: ixp4xx: Fix up the Netgear WG302 device tree
Link: https://lore.kernel.org/r/CACRpkdaMk+XECwhXJYeiF8SMU6cQsj_dk8gGMoPE3zAURAPqTw@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Ux500 DTS updates for the v5.18 kernel cycle:
- Add battery thermal zones so we can monitor the battery temperature
- Enable charging options on AB8505
- Fix up all the AB8500 and AB8505 nodes in accordance with the new
schema.
- Fix the mounting matrix for the Janice phone.
* tag 'ux500-dts-v5.18-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: dts: ux500: Correct Janice accel mount matrix
ARM: dts: ux500: Update AB850[05] nodes
ARM: dts: AB8505: Enable charging options
ARM: dts: ux500: Add battery thermal zones and NTCs
Link: https://lore.kernel.org/r/CACRpkdaDcEqtSnWzRBnBHVweh2n=Dj3meHG9LND+K0Czb9ORGg@mail.gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Renesas DT binding updates for v5.18
- Document support for the new RZ/V2L SoC and the RZ/V2L SMARC EVK
board.
* tag 'renesas-dt-bindings-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
dt-bindings: power: renesas,rzg2l-sysc: Document RZ/V2L SoC
dt-bindings: arm: renesas: Document Renesas RZ/V2L SoC on SMARC EVK
Link: https://lore.kernel.org/r/cover.1644587209.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Renesas ARM DT updates for v5.18
- External interrupt (INTC-EX) support for the R-Car V3U SoC,
- Initial support for the RZ/G2LC and RZ/V2L SoCs, and the RZ/G2LC and
RZ/V2L SMARC EVK development boards,
- Support for MAX9286 GMSL deserializers and GSML cameras on the Eagle
and Condor development boards,
- NAND support for the RZ/N1D SoC,
- DMA engine (SYS-DMAC) support for the R-Car S4-8 SoC,
- LVDS support for the R-Car M3-W+ SoC,
- HDMI output and 9-axis sensor support for the Kingfisher (ULCB
extension) board,
- MAX96712 GMSL serializer support for the Falcon development board,
- MOST network support for the R-Car H3, M3-W, M3-W+, M3-N, E3, and D3
SoCs,
- Miscellaneous fixes and improvements.
* tag 'renesas-arm-dt-for-v5.18-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel: (27 commits)
arm64: dts: renesas: rzg2lc-smarc: Use SW_SD0_DEV_SEL macro for eMMC/SDHI device selection
arm64: dts: renesas: rzg2lc-smarc: Enable CANFD channel 1
arm64: dts: renesas: rzg2lc-smarc: Enable SCIF1 on carrier board
arm64: dts: renesas: rzg2lc-smarc: Add macros for DIP-Switch settings
arm64: dts: renesas: rzg2l-smarc: Add common dtsi file
arm64: dts: renesas: rzg2lc-smarc: Enable microSD on SMARC platform
arm64: dts: renesas: rzg2lc-smarc-som: Enable eMMC on SMARC platform
arm64: dts: renesas: Add initial device tree for RZ/V2L SMARC EVK
arm64: dts: renesas: Add initial DTSI for RZ/V2L SoC
dt-bindings: clock: Add R9A07G054 CPG Clock and Reset Definitions
arm64: dts: renesas: ulcb/ulcb-kf: switch to use audio-graph-card2 for sound
arm64: dts: renesas: rcar-gen3: Add MOST devices
arm64: dts: renesas: Miscellaneous whitespace fixes
arm64: dts: renesas: falcon-csi-dsi: Add and connect MAX96712
arm64: dts: renesas: ulcb-kf: Add 9-asix sensor device
arm64: dts: renesas: ulcb-kf: Add KF HDMI output
arm64: dts: renesas: r8a77961: Add lvds0 device node
arm64: dts: renesas: r8a779f0: Add sys-dmac nodes
ARM: dts: r9a06g032: Describe the NAND controller
arm64: dts: renesas: Add GMSL cameras .dtsi
...
Link: https://lore.kernel.org/r/cover.1644587200.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Samsung pinctrl DTS and driver changes for v5.18
Conversion of Samsung pinctrl bindings to dtschema followed up with
alignment of DTS files to the dtschema.
The entire work consists of three parts but everything should be merged
at once to avoid dtschema check errors:
1. Samsung pinctrl driver change necessary to accept new DTS (driver
depends on node names and this has to be adjusted because of dtschema).
2. Conversion to dtschema which brings requirement of different naming
of the GPIO nodes.
3. DTS commits depending on driver (1) above, which convert all GPIO pin
bank names to new naming, required by dtschema.
This also includes few cleanups around DTS which are here to avoid
any merge conflicts.
The Samsung pinctrl driver changes are backwards compatible. However
the DTS changes (renaming nodes) could cause problems in out-of-tree or
other project implementations of the driver.
* tag 'samsung-dt-pinctrl-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (28 commits)
arm64: dts: exynos: use dedicated wake-up pinctrl compatible in ExynosAutov9
ARM: dts: s5pv210: align pinctrl with dtschema
ARM: dts: s3c64xx: align pinctrl with dtschema
ARM: dts: s3c24xx: align pinctrl with dtschema
arm64: dts: exynos: align pinctrl with dtschema in ExynosAutov9
arm64: dts: exynos: align pinctrl with dtschema in Exynos7
arm64: dts: exynos: align pinctrl with dtschema in Exynos5433
ARM: dts: exynos: align pinctrl with dtschema in Exynos542x/5800
ARM: dts: exynos: align pinctrl with dtschema in Exynos5410
ARM: dts: exynos: align pinctrl with dtschema in Exynos5260
ARM: dts: exynos: align pinctrl with dtschema in Exynos5250
ARM: dts: exynos: align pinctrl with dtschema in Exynos4412
ARM: dts: exynos: align pinctrl with dtschema in Exynos4210
ARM: dts: exynos: align pinctrl with dtschema in Exynos3250
ARM: dts: s3c64xx: drop unneeded pinctrl wake-up interrupt mapping
ARM: dts: exynos: simplify PMIC DVS pin configuration in Peach Pi
ARM: dts: exynos: override pins by label in Peach Pi
ARM: dts: exynos: simplify PMIC DVS pin configuration in Peach Pit
ARM: dts: exynos: override pins by label in Peach Pit
ARM: dts: exynos: simplify PMIC DVS pin configuration in Odroid XU
...
Link: https://lore.kernel.org/r/20220129115352.13274-1-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Samsung DTS ARM64 changes for v5.18
1. Minor improvements and dtschema fixes (node names, properties).
2. Fix issues pointed out by DT schema checks:
- Add necessary clock controller inputs on Exynos7.
- Add USB DWC3 supplies.
- Drop old syscon phandle on Exynos5433.
3. Add initial Exynos850 support and WinLink E850-96 board using it.
* tag 'samsung-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos: adjust USB DRD clocks with dtschema in Exynos7
arm64: dts: exynos: drop unneeded syscon phandle in Exynos5433 LPASS
arm64: dts: exynos: align pl330 node name with dtschema
arm64: dts: exynos: Add initial E850-96 board support
arm64: dts: exynos: Add initial Exynos850 SoC support
arm64: dts: exynos: add USB DWC3 supplies to Espresso board
arm64: dts: exynos: add necessary clock inputs in Exynos7
arm64: dts: exynos: Align MAX77843 nodes with dtschema on TM2
Link: https://lore.kernel.org/r/20220209145226.184375-2-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Samsung DTS ARM changes for v5.18
1. Minor improvements and dtschema fixes (node names, properties).
2. Fix issues pointed out by DT schema checks:
- Add necessary clock controller inputs on Exynos5260.
- Drop unsupported regulators on Odroid XU.
- Add USB DWC3 supplies.
- Drop old thermal properties from Exynos4210.
3. Add support for Samsung Chagall WiFi (Exynos5420, Samsung Galaxy Tab
S 10.5", SM-T800 ) and a similar Samsung Klimt WiFi (Samsung Galaxy
Tab S 8.4").
4. Add battery to Samsung P4Nnote (Exynos4412, Samsung Galaxy Note
10.1).
* tag 'samsung-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (22 commits)
ARM: dts: exynos: use generic node name for LPDDR3 timings in Odroid
ARM: dts: exynos: add charger and battery to p4note
ARM: dts: exynos: update dma node name with dtschema
ARM: dts: exynos: use define for TMU clock on Exynos4412
ARM: dts: exynos: drop old thermal properties from Exynos4210
ARM: dts: exynos: add fake USB DWC3 supplies to SMDK5410
ARM: dts: exynos: add USB DWC3 supplies to SMDK5420
ARM: dts: exynos: add USB DWC3 supplies to Chromebook Peach Pi
ARM: dts: exynos: add USB DWC3 supplies to Chromebook Peach Pit
ARM: dts: exynos: add USB DWC3 supplies to ArndaleOcta
ARM: dts: exynos: add USB DWC3 supplies to Chromebook Spring
ARM: dts: exynos: add USB DWC3 supplies to Chromebook Snow
ARM: dts: exynos: add USB DWC3 supplies to SMDK5250
ARM: dts: exynos: add USB DWC3 supplies to Arndale
ARM: dts: exynos: Add support for Samsung Klimt WiFi
dt-bindings: arm: samsung: document Klimt WiFi board binding
ARM: dts: exynos: Add support for Samsung Chagall WiFi
dt-bindings: arm: samsung: document Chagall WiFi board binding
ARM: dts: exynos: drop unsupported MAX77802 regulators on Odroid XU
ARM: dts: exynos: add necessary clock controller inputs in Exynos5260
...
Link: https://lore.kernel.org/r/20220209145226.184375-1-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Tesla FSD ARM64 changes for v5.18
Add Tesla FSD SoC ARM64 platform: bindings, DTSI+DTS, maintainer's entry
and defconfig change. This brings and enables this new platform.
This includes clock controller bindings (header files with clock IDs)
which are shared also with Tesla FSD SoC clock controller pull request.
* tag 'tesla-dt64-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: fsd: Add SPI device nodes
arm64: defconfig: Enable Tesla FSD SoC
arm64: dts: fsd: Add initial pinctrl support
arm64: dts: fsd: Add initial device tree support
dt-bindings: clock: Document FSD CMU bindings
dt-bindings: clock: Add bindings definitions for FSD CMU blocks
dt-bindings: arm: add Tesla FSD ARM SoC
dt-bindings: add vendor prefix for Tesla
Link: https://lore.kernel.org/r/20220204154112.133723-2-krzysztof.kozlowski@canonical.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The OSMC Vero 4K+ device is based on the Amlogic S905D (P230)
reference design with the following specifications:
- 2GB DDR4 RAM
- 16GB eMMC
- HDMI 2.1 video
- S/PDIF optical output
- AV output
- 10/100/1000 Ethernet
- AP6255 Wireless (802.11 a/b/g/n/ac, BT 4.2)
- 2x USB 2.0 ports (1x OTG)
- IR receiver (internal)
- IR extender port (external)
- 1x micro SD card slot
- 1x Power LED (red)
- 1x Reset button (in AV jack)
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Tested-by: Chad Wagner <wagnerch42@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Link: https://lore.kernel.org/r/20220211105311.30320-4-christianshewitt@gmail.com
The GW7903 is based on the i.MX 8M Mini SoC featuring:
- LPDDR4 DRAM
- eMMC FLASH
- microSD connector with UHS support
- LIS2DE12 3-axis accelerometer
- Gateworks System Controller
- IMX8M FEC
- software selectable RS232/RS485/RS422 serial transceiver
- PMIC
- 2x off-board bi-directional opto-isolated digital I/O
- 1x M.2 A-E Key Socket and 1x MiniPCIe socket with USB2.0 and PCIe
(resistor loading to route PCIe/USB2 between M.2 and MiniPCIe socket)
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
infinity2m are running up to 1.2Ghz, this extends opp_table with the
corresponding frequencies and enable operating-points table for cpu1
Signed-off-by: Romain Perier <romain.perier@gmail.com>
The infinity3 has a slightly higher max frequency
compared to the infinity so extend the OPP table.
Co-authored-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Romain Perier <romain.perier@gmail.com>
Add an OPP table for the inifinity chips so
that cpu frequency scaling can happen.
Co-authored-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Romain Perier <romain.perier@gmail.com>
The second core also sources it's clock from the CPU PLL.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Romain Perier <romain.perier@gmail.com>
The CPU clock is sourced from the CPU PLL.
Link cpupll to the cpu so that frequency scaling can happen.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Romain Perier <romain.perier@gmail.com>
All MStar/SigmaStar ARMv7 SoCs have the CPU PLL at the same
place so add it to the base dtsi.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Romain Perier <romain.perier@gmail.com>
Add a binding description for the MStar/SigmaStar CPU PLL block.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Move the usb2_picophy1 and usb2_picophy2 nodes out of the soc section.
Since they are controlled via syscfg, there is no reg property needed,
which is required when having the node within the soc section.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Move the usb2_picophy1 and usb2_picophy2 nodes out of the soc section.
Since they are controlled via syscfg, there is no reg property needed,
which is required when having the node within the soc section.
Modification is done within stih410.dtsi and within related board
dts files (stih410-b2120.dts, stih410-b2260.dts).
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
The delta0 node within stih410.dtsi is identical to the
one already written within stih407-family.dtsi and included
within stih410.dtsi.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Move all nodes without reg property out of the soc section of
stih407-family.dtsi and DT including stih407-family.dtsi.
This avoid to set a <0> reg property.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Move quadfs and a9-mux clocks nodes into clockgen nodes so
that they can get the reg property from the parent node and
ensure only one node has the address.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Move quadfs and a9-mux clocks nodes into clockgen nodes so
that they can get the reg property from the parent node and
ensure only one node has the address.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Move quadfs and a9-mux clocks nodes into clockgen nodes so
that they can get the reg property from the parent node and
ensure only one node has the address.
Signed-off-by: Alain Volmat <avolmat@me.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
The Global Control Registers (GCR) are a block of registers in Nuvoton
SoCs that expose misc functionality such as chip model and version
information or pinmux settings.
This patch adds a GCR node to nuvoton-wpcm450.dtsi in preparation for
enabling pinctrl on this SoC.
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Link: https://lore.kernel.org/r/20220129115228.2257310-4-j.neuschaefer@gmx.net
Signed-off-by: Joel Stanley <joel@jms.id.au>
A nuvoton,*-gcr node is present in nuvoton-common-npcm7xx.dtsi and will
be added to nuvoton-wpcm450.dtsi. It is necessary for the NPCM7xx and
WPCM450 pinctrl drivers, and may later be used to retrieve SoC model and
version information.
This patch adds a binding to describe this node.
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220129115228.2257310-2-j.neuschaefer@gmx.net
Signed-off-by: Joel Stanley <joel@jms.id.au>
This adds the defines for the power domains provided by the HSIO
blk-ctrl on the i.MX8MP.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The Gateaway 7001 has a serial port alias for serial1, this has
proven detrimental on the WG302 so remove it on this machine
as well.
Drop in a small comment that this machine is based on IXP422.
Cc: Zoltan HERPAI <wigyori@uid0.hu>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
We have at least 0x30 registers in the IXP42x syscon as
register 0x2c is actively used to read platform features.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The version we can support (because of access to the hardware)
is WG302v1, so rename the file and make the following
modifications:
- We have 32MB memory not 16MB
- The default console speed is 9600 baud so use this
- The device has no ATA disk nor USB so drop the /dev/sda1
default mount, this needs to mount ramdisk or NFS
- Both serial0 and serial1 cannot be assigned with aliases,
just assign serial0
- The Flash is just 8MB so augment the size
- The Flash FIS index is at eraseblock 0x3f
- The PHY is at MDIO address 30
Tested by bringing the Netgear WG302v1 up to userspace using
initramfs appended to the kernel and downloaded over TFTP,
then ifconfig to bring up eth0 and pinging the host. All
works fine including SSH into the device from the host.
Cc: Zoltan HERPAI <wigyori@uid0.hu>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The new YAML device tree bindings gives new and proper names
to several of the AB850[05] nodes and redefines the way we
use numbering on PWMs to use reg.
Update all the DTS nodes accordingly.
Add the missing thermal node to the AB8505.
Drop the debugfs nodes because these are not real devices.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
These are not disabled on the AB8500 and after testing we
see they work fine, so enable them on AB8505 too.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
