The gpiod_to_irq() function never returns zero. It returns negative
error codes or a positive IRQ number. Update the checking to check
for negatives.
Fixes: 41bb142a40 ("platform: cznic: turris-omnia-mcu: Add support for MCU provided TRNG")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Reviewed-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Qualcomm driver updates for v6.12
Support is added for making SCM driver configure the system either for a
full or minimal ramdump following a system crash. The ramdump mode is
changed from being enable-only to enable/disable as requested.
The QSEECOM uefisecapp interface is allow-listed on Surface Laptop 7 and
Lenovo Thinkpad T14s, providing EFI variable access.
The change to match the SMD RPM driver based on the SMD channel name is
reverted, in favor of stepping back to OF-based matching, as a means to
get module autoloading to work properly.
AOSS, APR, ICE, OCMEM, PBS and SMP2P drivers has error handling cleaned
up using scoped resources.
Trace events are added to the BWMON and SMP2P drivers, for better
insights into their operations.
The X1E LLCC configuration data is updated based on recommended values.
A number of platforms are added to the in-kernel PD-mapper.
SocInfo driver is extended with IDs from SM7325, QCS8275 and QCS8300
families.
* tag 'qcom-drivers-for-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (33 commits)
firmware: qcom: scm: Allow QSEECOM on Surface Laptop 7 models
dt-bindings: soc: qcom: qcom,pmic-glink: Document SM7325 compatible
soc: qcom: pd_mapper: Add SM7325 compatible
soc: qcom: socinfo: Add Soc IDs for SM7325 family
dt-bindings: arm: qcom,ids: Add IDs for SM7325 family
soc: qcom: socinfo: add QCS8275/QCS8300 SoC ID
dt-bindings: arm: qcom,ids: add SoC ID for QCS8275/QCS8300
soc: qcom: smp2p: use scoped device node handling to simplify error paths
soc: qcom: pbs: use scoped device node handling to simplify error paths
soc: qcom: ocmem: use scoped device node handling to simplify error paths
soc: qcom: ice: use scoped device node handling to simplify error paths
soc: qcom: aoss: simplify with scoped for each OF child loop
soc: qcom: apr: simplify with scoped for each OF child loop
soc: qcom: smd-rpm: add qcom,smd-rpm compatible
dt-bindings: soc: qcom: smd-rpm: add generic compatibles
Revert "soc: qcom: smd-rpm: Match rpmsg channel instead of compatible"
firmware: qcom: scm: Add multiple download mode support
firmware: qcom: scm: Refactor code to support multiple dload mode
soc: qcom: pd_mapper: Add more older platforms without domains
soc: qcom: pd_mapper: Add X1E80100
...
Link: https://lore.kernel.org/r/20240904193042.15118-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Microchip AT91 SoC updates for v6.12
It contains:
- support for the Microchip SAM9X7 SoC:
-- power management
-- SoC identification
-- sysreg documentation updates
-- necessary Kconfig updates
* tag 'at91-soc-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
ARM: at91: Kconfig: add config flag for SAM9X7 SoC
ARM: at91: add support in SoC driver for new sam9x7
ARM: at91: pm: add sam9x7 SoC init config
ARM: at91: pm: add support for sam9x7 SoC family
dt-bindings: atmel-sysreg: add sam9x7
Link: https://lore.kernel.org/r/20240901133110.2038675-3-claudiu.beznea@tuxon.dev
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reset controller updates for v6.12
Use get_device()/put_device() to keep reset controller devices alive
while their reset controls are acquired.
Enable support for the Amlogic T7 SoC reset controller.
Remove unused EyeQ reset bindings and add a reset controller driver
to be instantiated as auxiliary device by the EyeQ clock driver.
Fix OF node leaks in the k210 and berlin probe() error paths.
Add some simplifications and cleanup in the core, lcp18xx driver, and
uniphier bindings.
* tag 'reset-for-v6.12' of git://git.pengutronix.de/pza/linux:
reset: eyeq: add platform driver
Revert "dt-bindings: reset: mobileye,eyeq5-reset: add bindings"
reset: reset-meson: Add support for Amlogic T7 SoC reset controller
dt-bindings: reset: Add Amlogic T7 reset controller
reset: core: add get_device()/put_device on rcdev
reset: lpc18xx: simplify with devm_clk_get_enabled()
reset: lpc18xx: simplify with dev_err_probe()
reset: simplify locking with guard()
reset: k210: fix OF node leak in probe() error path
reset: berlin: fix OF node leak in probe() error path
dt-bindings: reset: socionext,uniphier-glue-reset: add top-level constraints
Link: https://lore.kernel.org/r/20240904103921.1479579-1-p.zabel@pengutronix.de
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
TI SoC driver updates for v6.12
- pm33xx/knav_qmss_queue/pruss: Cleanups around device_node scope based cleanups
- knav: Additional fixes around of property
- k3-ringacc: Optimizations for data structure
* tag 'ti-driver-soc-for-v6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux:
soc: ti: pm33xx: do device_node auto cleanup
soc: ti: knav_qmss_queue: do device_node auto cleanup
soc: ti: pruss: do device_node auto cleanup
soc: ti: pruss: factor out memories setup
soc: ti: knav: Use of_property_read_variable_u32_array()
soc: ti: knav: Drop unnecessary check for property presence
soc: ti: k3-ringacc: Constify struct k3_ring_ops
Link: https://lore.kernel.org/r/20240903155632.525twuumykwnfkiz@subtitle
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
QMC driver requires fsl_soc.h to use function get_immrbase().
This header is provided by powerpc architecture and the functions
it declares are defined only when FSL_SOC is selected.
Today the dependency is the following:
depends on CPM1 || QUICC_ENGINE || \
(FSL_SOC && (CPM || QUICC_ENGINE) && COMPILE_TEST)
This dependency tentatively ensure that FSL_SOC is there when doing a
COMPILE_TEST.
CPM1 is only selected by PPC_8xx and cannot be selected manually.
CPM1 selects FSL_SOC
QUICC_ENGINE on the other hand can be selected by ARM or ARM64 which
doesn't select FSL_SOC. QUICC_ENGINE can also be selected with just
COMPILE_TEST.
It is therefore possible to end up with CPM_QMC selected
without FSL_SOC.
So fix it by making it depend on FSL_SOC at all time.
The rest of the above dependency is the same as the one for CPM_TSA on
which CPM_QMC also depends, so it can go away, leaving only a simple
dependency on FSL_SOC.
Reported-by: Stephen Rothwell <sfr@canb.auug.org.au>
Closes: https://lore.kernel.org/lkml/20240904104859.020fe3a9@canb.auug.org.au/
Fixes: 8655b76b70 ("soc: fsl: cpm1: qmc: Handle QUICC Engine (QE) soft-qmc firmware")
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Acked-by: Herve Codina <herve.codina@bootlin.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Herve Codina says:
================
This series add support for the QUICC Engine (QE) version of TSA and QMC
components.
CPM1 version is already supported and, as the QE version of those
component are pretty similar to the CPM1 version, the series extend
the already existing drivers to support for the QE version.
The TSA and QMC components are tightly coupled and so the series
provides modifications on both components.
Of course, this series can be split if it is needed. Let me know.
The series is composed of:
- Patches 1 and 2: Fixes related to TRNSYNC in the QMC driver
- Patches 3..6: Fixes of checkpatch detected issues in the TSA driver
- Patch 7: The QE TSA device-tree binding
- Patches 8..13: TSA driver preparations for adding support for QE
- Patches 14 and 15: The support for QE in TSA + MAINTAINERS update
- Patch 16: A TSA API improvement needed for the QE QMC driver
- Patch 17: A clarification in the QE QMC driver
- Patches 18..22: Fixes of checkpatch detected issues in the QMC driver
- Patch 23: The QE QMC device-tree binding
- Patches 24..31: QMC driver preparations for adding support for QE
- Patches 32 and 33: Missing features additions in QE code
- Patches 34..36: The QMC support for QE in QMC + MAINTAINERS update
Compared to the previous iteration, this v2 series updates device-tree
bindings and fixes issues detected by kernel test robots.
Related to the QE QMC device-tree binding, I kept the unit address in
decimal and the 3 compatible strings.
================
Link: https://lore.kernel.org/r/20240808071132.149251-1-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Tested-by: Christophe Leroy <christophe.leroy@csgroup.eu>
This warning was added by commit 07f86917a4 ("soc/fsl/qbman: Use
shared-dma-pool for QMan private memory allocations") but
RESERVEDMEM_OF_DECLARE usage was removed by
commit 3e62273ac6 ("soc: fsl: qbman: Remove RESERVEDMEM_OF_DECLARE
usage") . For non-popwerpc platforms, such as ls1043, this warning
is redundant. ls1043 itself uses shared-dma-mem.
Fixes: 3e62273ac6 ("soc: fsl: qbman: Remove RESERVEDMEM_OF_DECLARE usage")
Signed-off-by: Xiaolei Wang <xiaolei.wang@windriver.com>
Link: https://lore.kernel.org/r/20240802021651.3854295-1-xiaolei.wang@windriver.com
[chleroy: Added more details in commit message]
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Add support for the QMC (QUICC Multichannel Controller) available in
some PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321.
This QE QMC is similar to the CPM QMC except that it uses UCCs (Unified
Communication Controllers) instead of SCCs (Serial Communication
Controllers). Also, compared against the CPM QMC, this QE QMC does not
use a fixed area for the UCC/SCC parameters area but it uses a dynamic
area allocated and provided to the hardware at runtime.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-35-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
The PUSHSCHED command is missing in the QE header file.
This command is supported on MPC8321 and is used to modify the start
address for the task running on a given peripheral. It is needed for the
QMC in order to perform the re-initialization procedure and so, ensure
the correct UCC setup in that case.
Simply add the missing command in the commands list available in the QE
header file.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-34-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Current code handles CPM1 version of QMC. Even if GSMRL is specific to
the CPM1 version, the exact same purpose and format register (GUMRL) is
present in the QUICC Engine (QE) version of QMC. Compared to the QE
version, the values defined for the mode bitfield are different and the
0x0A value defined for the QMC mode is CPM1 specific.
In order to prepare the support for the QE version, rename this bitfield
value to clearly identify it as CPM1 specific.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-31-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Current code handles the CPM1 version of QMC and initialize the QMC used
SCC. The QUICC Engine (QE) version uses an UCC (Unified Communication
Controllers) instead of the SCC (Serial Communication Controllers) used
in the CPM1 version. These controllers serve the same purpose and are
used in the same way but their inializations are slightly different.
In order to prepare the support for QE version of QMC, introduce
qmc_init_xcc() to initialize theses controllers (UCC in QE and SCC in
CPM1) and isolate the CPM1 specific SCC initialization in a specific
function.
Also introduce qmc_exit_xcc() for consistency to revert operations done
in qmc_init_xcc().
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-28-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Current code handles the CPM1 version of QMC. Resources initialisations
(i.e. retrieving base addresses and offsets of different parts) will
be slightly different in the QUICC Engine (QE) version. Indeed, in QE
version, some resources need to be allocated and are no more "staticaly"
defined.
In order to prepare the support for QE version, introduce
qmc_init_resource() to initialize those resources and isolate the CPM1
specific operations in a specific function.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-27-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Current code handles CPM1 version of QMC. In the QUICC Engine (QE)
version, some operations done at probe() need to be done in a different
order.
In order to prepare the support for the QE version, changed the sequence
of operation done at probe():
- Retrieve the tsa_serial earlier, before initializing resources.
- Group SCC initialisation and do this initialization when it is really
needed in the probe() sequence.
Having the QE compatible sequence in the CPM1 version does not lead to
any issue and works correctly without any regressions.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-26-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Current code handles CPM1 version of QMC. Some hardcoded values are used
several times to initialize the QMC state machine. In the QUICC Engine
(QE) version of QMC, these values are different.
In order to prepare the support for the QE version of QMC and avoid the
copy of the hardcoded values, introduce the qmc_data structure to define
these version specific values.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-25-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Add support for the QMC (QUICC Multichannel Controller) available in
some PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321.
This QE QMC is similar to the CPM QMC except that it uses UCCs (Unified
Communication Controllers) instead of SCCs (Serial Communication
Controllers). Also, compared against the CPM QMC, this QE QMC does not
use a fixed area for the UCC/SCC parameters area but it uses a dynamic
area allocated and provided to the hardware at runtime.
Last point, the QE QMC can use a firmware to have the QMC working in
'soft-qmc' mode.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-24-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Add support for the time slot assigner (TSA) available in some
PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321.
The QE TSA is similar to the CPM1 TSA except that it uses UCCs (Unified
Communication Controllers) instead of SCCs (Serial Communication
Controllers).
Also, compared against the CPM1 TSA, this QE TSA can handle up to 4 TDMs
instead of 2 and allows to configure the logic level of sync signals.
At a lower level, compared against CPM TSA implementation, some
registers are slightly different even if same features are present.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-15-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Current code handles the CPM1 version of TSA. Connecting and
disconnecting the SCC to/from the TSA consists in handling SICR register
which is CPM1 specific. The connection and disconnection operation in
the QUICC Engine (QE) version are slightly different.
In order to prepare the support for the QE version, clearly identify
SICR register as specific to CPM1 and isolate its handling done in
connect and disconnect functions.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-13-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Current code handles the CPM1 version of TSA. Setting up TSA consists in
handling SIMODE and SIGMR registers. These registers are CPM1 specific.
Setting up the QUICC Engine (QE) version of TSA is slightly different.
In order to prepare the support for QE version, clearly identify these
registers as CPM1 compatible and isolate their handling in a CPM1
specific function.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-12-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Add support for the time slot assigner (TSA) available in some
PowerQUICC SoC that uses a QUICC Engine (QE) block such as MPC8321.
This QE TSA is similar to the CPM TSA except that it uses UCCs (Unified
Communication Controllers) instead of SCCs (Serial Communication
Controllers). Also, compared against the CPM TSA, this QE TSA can handle
up to 4 TDMs instead of 2 and allows to configure the logic level of
sync signals.
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/20240808071132.149251-8-herve.codina@bootlin.com
Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
