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Author SHA1 Message Date
Richard Acayan
fbf7cfa3ea arm64: dts: qcom: sdm670-google-sargo: enable gpu 
Enable the A615 GPU and GMU for the Pixel 3a. It has zap firmware, so
add that in as well.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Link: https://lore.kernel.org/r/20240806214452.16406-11-mailingradian@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 12:57:40 -06:00
Richard Acayan
cd89483a13 arm64: dts: qcom: sdm670: add gpu 
The Snapdragon 670 has the Adreno A615 GPU. Add it along with its device
tree dependencies.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Link: https://lore.kernel.org/r/20240806214452.16406-10-mailingradian@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 12:57:40 -06:00
Jie Gan
0f43254763 arm64: dts: qcom: qcs8300: Add coresight nodes 
Add following coresight components for QCS8300 platform.
It includes CTI, dummy sink, dynamic Funnel, Replicator, STM,
TPDM, TPDA and TMC ETF.

Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241219024208.3462358-1-quic_jiegan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 12:36:53 -06:00
Srinivas Kandagatla
12805b0f99 arm64: dts: qcom: x1e78100-t14s: add sound support 
Add support for audio on Lenovo T14s laptop, coming with two speakers,
audio jack and two digital microphones.

This is very early work, not yet complete:
1. 2x speakers: work OK.
2. 2x digital microphones: work OK.
3. Headset (audio jack) recording: does not work.
4. Headphones playback (audio jack): channels are intermixed.

[krzysztof: correct DMIC routing and vamacro pinctrl, re-order nodes,
 add commit msg]

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Co-developed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241203111229.48967-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 12:31:25 -06:00
Dmitry Baryshkov
cc47b12315 arm64: dts: qcom: sm8350-hdk: enable IPA 
Although the HDK has no radio, the IPA part is still perfectly usable
(altough it doesn't register any real networking devices). Enable it to
make it possible to test IPA on this platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230310203438.1585701-1-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 10:19:49 -06:00
Jianhua Lu
8b14c06486 arm64: dts: qcom: sm8250-xiaomi-elish: Add bluetooth node 
Add bluetooth node and this bluetooth module is connected to uart.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Jianhua Lu <lujianhua000@gmail.com>
Link: https://lore.kernel.org/r/20241201135716.141691-3-lujianhua000@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:51:45 -06:00
Jianhua Lu
1993f02553 arm64: dts: qcom: sm8250-xiaomi-elish: Add wifi node 
Add wifi node and this wifi module is connected to PCIe port.
The following is qca6390 probe message:
  ath11k_pci 0000:01:00.0: Adding to iommu group 12
  ath11k_pci 0000:01:00.0: BAR 0 [mem 0x60400000-0x604fffff 64bit]: assigned
  ath11k_pci 0000:01:00.0: enabling device (0000 -> 0002)
  ath11k_pci 0000:01:00.0: MSI vectors: 32
  ath11k_pci 0000:01:00.0: qca6390 hw2.0
  ath11k_pci 0000:01:00.0: chip_id 0x0 chip_family 0xb board_id 0xff soc_id 0xffffffff
  ath11k_pci 0000:01:00.0: fw_version 0x10121492 fw_build_timestamp 2021-11-04 11:23 fw_build_id

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Jianhua Lu <lujianhua000@gmail.com>
Link: https://lore.kernel.org/r/20241201135716.141691-2-lujianhua000@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:51:45 -06:00
Jianhua Lu
6e4ec5f694 arm64: dts: qcom: sm8250-xiaomi-elish: Add qca6390-pmu node 
Add qca6390-pmu node, which is used to manage power supply sequence for wifi and
bluetooth on sm8250 soc based devices.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Jianhua Lu <lujianhua000@gmail.com>
Link: https://lore.kernel.org/r/20241201135716.141691-1-lujianhua000@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:51:45 -06:00
Konrad Dybcio
86348c7587 arm64: dts: qcom: sa8775p: Use valid node names for GPI DMAs 
As pointed out by Intel's robot, the node name doesn't adhere to
dt-bindings.

Fix errors like this one:

qcs9100-ride.dtb: qcom,gpi-dma@800000: $nodename:0: 'qcom,gpi-dma@800000' does not match '^dma-controller(@.*)?$'

Fixes: 34d17ccb5d ("arm64: dts: qcom: sa8775p: Add GPI configuration")
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202411080206.vFLRjIBZ-lkp@intel.com/
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241107-topic-sa8775_dma-v1-1-eb633e07b007@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:50:49 -06:00
Soutrik Mukhopadhyay
9767920a7a arm64: dts: qcom: sa8775p-ride: Enable Display Port 
The Qualcomm SA8775P platform comes with 2 DisplayPort controllers
for each mdss. edp0 and edp1 correspond to the DP controllers of
mdss0, whereas edp2 and edp3 correspond to the DP controllers of
mdss1. This change enables only the DP controllers, DPTX0 and DPTX1
alongside their corresponding PHYs of mdss0, which have been
validated.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241125105747.6595-3-quic_mukhopad@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:50:49 -06:00
Soutrik Mukhopadhyay
e1e3e5673f arm64: dts: qcom: sa8775p: add DisplayPort device nodes 
Add device tree nodes for the DPTX0 and DPTX1 controllers
with their corresponding PHYs found on Qualcomm SA8775P SoC.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Link: https://lore.kernel.org/r/20241125105747.6595-2-quic_mukhopad@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:50:49 -06:00
Yuvaraj Ranganathan
cc9d29aad8 arm64: dts: qcom: qcs8300: enable the inline crypto engine 
Add an ICE node to qcs8300 SoC description and enable it by adding a
phandle to the UFS node.

Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com>
Link: https://lore.kernel.org/r/20241125065801.1751256-3-quic_yrangana@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:50:49 -06:00
Yuvaraj Ranganathan
f1b359bdf0 arm64: dts: qcom: qcs8300: add TRNG node 
The qcs8300 SoC has a True Random Number Generator, add the node with
the correct compatible set.

Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241125064317.1748451-3-quic_yrangana@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:50:49 -06:00
Petr Vorel
507aae9a35 arm64: dts: qcom: msm8994-angler: Enable power key, volume up/down 
Signed-off-by: Petr Vorel <petr.vorel@gmail.com>
Link: https://lore.kernel.org/r/20241123221708.862901-1-petr.vorel@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:50:49 -06:00
Manikanta Mylavarapu
825b203296 arm64: dts: qcom: ipq5424: Add watchdog node 
Add the watchdog node for IPQ5424 SoC.

Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Link: https://lore.kernel.org/r/20241121051951.1776250-3-quic_mmanikan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:50:49 -06:00
Ling Xu
ac92750c03 arm64: dts: qcom: qcs8300: Add ADSP and CDSP0 fastrpc nodes 
Add ADSP and CDSP0 fastrpc nodes for QCS8300 platform.

Signed-off-by: Ling Xu <quic_lxu5@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241119120635.687936-1-quic_lxu5@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:50:43 -06:00
Maulik Shah
736f50489e arm64: dts: qcom: sa8775p: Add CPUs to psci power domain 
Commit 4f79d0deae ("arm64: dts: qcom: sa8775p: add CPU idle states")
already added cpu and cluster idle-states but have not added CPU devices
to psci power domain without which idle states do not get detected.

Add CPUs to psci power domain.

Fixes: 4f79d0deae ("arm64: dts: qcom: sa8775p: add CPU idle states")
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/20241112-sa8775p_cpuidle-v1-1-66ff3ba72464@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:34:12 -06:00
Richard Acayan
44d2a25269 arm64: dts: qcom: sdm670-google-sargo: add flash leds 
The Pixel 3a has two identical flash LEDs. Add them together.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241112024050.669578-9-mailingradian@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:28:33 -06:00
Richard Acayan
9b2955bae7 arm64: dts: qcom: pm660l: add flash leds 
The PM660L has support for QPNP flash LEDs. Add them to the device tree.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Link: https://lore.kernel.org/r/20241112024050.669578-8-mailingradian@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:28:33 -06:00
Konrad Dybcio
a8d18df5a5 arm64: dts: qcom: sa8775p: Use a SoC-specific compatible for GPI DMA 
The commit adding these nodes did not use a SoC-specific node, fix that
to comply with bindings guidelines.

Fixes: 34d17ccb5d ("arm64: dts: qcom: sa8775p: Add GPI configuration")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241108-topic-sa8775_dma2-v1-2-1d3b0d08d153@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:28:02 -06:00
Mahadevan
2f39d2d46c arm64: dts: qcom: sa8775p: add display dt nodes for MDSS0 and DPU 
Add devicetree changes to enable MDSS0 display-subsystem its
display-controller(DPU) for Qualcomm SA8775P platform.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
Link: https://lore.kernel.org/r/20241019-patchv3_1-v5-5-d2fb72c9a845@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:20:03 -06:00
Taniya Das
727dc481e5 arm64: dts: qcom: sa8775p: Add support for clock controllers 
Add support for video, camera, display0 and display1 clock controllers
on SA8775P. The dispcc1 will be enabled based on board requirements.

Reviewed-by: Jagadeesh Kona <quic_jkona@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241025-sa8775p-mm-v4-resend-patches-v6-2-329a2cac09ae@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:20:03 -06:00
Taniya Das
30f7dfd2c4 arm64: dts: qcom: sa8775p: Update sleep_clk frequency 
Fix the sleep_clk frequency is 32000 on SA8775P.

Fixes: 603f96d4c9 ("arm64: dts: qcom: add initial support for qcom sa8775p-ride")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241025-sa8775p-mm-v4-resend-patches-v6-1-329a2cac09ae@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:20:03 -06:00
Rakesh Kota
abc0c29f5e arm64: dts: qcom: qcm6490-idp: Allow UFS regulators load/mode setting 
The UFS driver expects to be able to set load (and by extension, mode)
on its supply regulators. Add the necessary properties to make that
possible.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Rakesh Kota <quic_kotarake@quicinc.com>
Link: https://lore.kernel.org/r/20241017122858.3664474-1-quic_kotarake@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:20:03 -06:00
Marek Vasut
02e784c502 arm64: dts: qcom: msm8996-xiaomi-gemini: Fix LP5562 LED1 reg property 
The LP5562 led@1 reg property should likely be set to 1 to match
the unit. Fix it.

Fixes: 4ac46b3682 ("arm64: dts: qcom: msm8996: xiaomi-gemini: Add support for Xiaomi Mi 5")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241006022012.366601-1-marex@denx.de
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:20:03 -06:00
Konrad Dybcio
703b23b802 arm64: dts: qcom: qcs6490-rb3gen2: Configure onboard LEDs 
RB3 Gen2 has a trio of LEDs connected to the PM8350C's Light Pulse
Generator. Describe them.

Use the "red channel" as a panic indicator by default.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
[bjorn: Corrected colors]
Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241004-rb3gen2-leds-v1-2-437cdbb4f6c0@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:20:03 -06:00
Konrad Dybcio
2526297626 arm64: dts: qcom: pmk8350: Add more SDAM slices 
The downstream tree described more SDAM slices on the PMIC. Some of
them are actually required by other peripherals, whereas other are nice
to add for hardware description purposes.

Add them in.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241004-rb3gen2-leds-v1-1-437cdbb4f6c0@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 23:20:03 -06:00
devi priya
438d05fb9b arm64: dts: qcom: ipq9574: Enable PCIe PHYs and controllers 
Enable the PCIe controller and PHY nodes corresponding to RDP 433.

Signed-off-by: devi priya <quic_devipriy@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/r/20240801054803.3015572-4-quic_srichara@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 22:12:08 -06:00
devi priya
d80c7fbfa9 arm64: dts: qcom: ipq9574: Add PCIe PHYs and controller nodes 
Add PCIe0, PCIe1, PCIe2, PCIe3 (and corresponding PHY) devices
found on IPQ9574 platform. The PCIe0 & PCIe1 are 1-lane Gen3
host whereas PCIe2 & PCIe3 are 2-lane Gen3 host.

Signed-off-by: devi priya <quic_devipriy@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/r/20240801054803.3015572-3-quic_srichara@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 22:12:07 -06:00
Anthony Ruhier
7069abcd53 arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Add lid switch 
Add the lid switch for the Lenovo Yoga Slim 7x.

Other x1e80100 laptops use the GPIO pin 92 only, however on the Yoga
Slim 7x this pin seems to be bridged with the pin 71. By default, the
pin 71 is set as output-high, which blocks any event on pin 92.

This patch sets the pin 71 as output-disable and sets the LID switch on
pin 92. This is aligned with how they're configured on Windows:
    GPIO  71 | 0xf147000 | in | func0 | hi | pull up   | 16 mA
    GPIO  92 | 0xf15c000 | in | func0 | lo | no pull   |  2 mA

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Maya Matuszczyk <maccraft123mc@gmail.com>
Signed-off-by: Anthony Ruhier <aruhier@mailbox.org>
Link: https://lore.kernel.org/r/20241219-patch-lenovo-yoga-v3-1-9c4a79068141@mailbox.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 22:03:40 -06:00
Luca Weiss
be2f81eaa2 arm64: dts: qcom: sm6350: Fix uart1 interconnect path 
The path MASTER_QUP_0 to SLAVE_EBI_CH0 would be qup-memory path and not
qup-config. Since the qup-memory path is not part of the qcom,geni-uart
bindings, just replace that path with the correct path for qup-config.

Fixes: b179f35b88 ("arm64: dts: qcom: sm6350: add uart1 node")
Cc: stable@vger.kernel.org
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241220-sm6350-uart1-icc-v1-1-f4f10fd91adf@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 21:59:06 -06:00
Konrad Dybcio
5deec162b2 dt-bindings: arm: qcom: Add X1P42100 SoC & CRD 
The X1 family is split into two parts: the 10- and 12-core parts are
variants of the same silicon with different fusing, whereas the 8-core
ones are a separate design. Thankfully, the software interface is only
barely different, letting us reuse much of the existing X1 work.

Add X1P42100 SoC (and the CRD based on it) as a representative of the
8-core series.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20241221-topic-x1p4_soc-v1-2-55347831d73c@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 21:55:29 -06:00
Konrad Dybcio
13dcb0eff1 dt-bindings: arm: qcom-soc: Extend X1E prefix match for X1P 
The X1 series includes SoCs like X1P42100. Extend the pattern x1e match
to x1[ep] to also include these.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20241221-topic-x1p4_soc-v1-1-55347831d73c@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 21:55:29 -06:00
Yuvaraj Ranganathan
a86d844099 arm64: dts: qcom: qcs8300: add QCrypto nodes 
Add the QCE and Crypto BAM DMA nodes.

Signed-off-by: Yuvaraj Ranganathan <quic_yrangana@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241223110936.3428125-1-quic_yrangana@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-25 21:50:27 -06:00
Sibi Sankar
c074fc2220 arm64: dts: qcom: x1e001de-devkit: Enable SD card support 
The SD card slot found on the X1E001DE Snapdragon Devkit for windows
board is controlled by SDC2 instance, so enable it.

Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241025123551.3528206-3-quic_sibis@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-20 21:54:04 -06:00
Abel Vesa
ab8f487d2f arm64: dts: qcom: x1e80100-qcp: Enable SD card support 
One of the SD card slots found on the X Elite QCP board is
controlled by the SDC2.

Enable it and describe the board specific resources.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20241212-x1e80100-qcp-sdhc-v4-2-a74c48ee68a3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-20 21:52:51 -06:00
Abel Vesa
ffb21c1e19 arm64: dts: qcom: x1e80100: Describe the SDHC controllers 
The X Elite platform features two SDHC v5 controllers.

Describe the controllers along with the pin configuration in TLMM
for the SDC2, since they are hardwired and cannot be muxed to any
other function. The SDC4 pin configuration can be muxed to different
functions, so leave those to board specific dts.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20241212-x1e80100-qcp-sdhc-v4-1-a74c48ee68a3@linaro.org
[bjorn: Replaced 0s with QCOM_ICC_TAG_ALWAYS]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-20 21:52:23 -06:00
Lijuan Gao
89fc83a947 arm64: dts: qcom: qcs615: Add CPU and LLCC BWMON support 
Add CPU and LLCC BWMON nodes and their corresponding opp tables to
support bandwidth monitoring on QCS615 SoC. This is necessary to enable
power management and optimize system performance from the perspective of
dynamically changing LLCC and DDR frequencies.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241218-add_bwmon_support_for_qcs615-v1-2-680d798a19e5@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-20 21:46:50 -06:00
Xin Liu
3d0d8c8989 arm64: dts: qcom: qcs8300: Add watchdog node 
Add the watchdog node for QCS8300 SoC.

Signed-off-by: Xin Liu <quic_liuxin@quicinc.com>
 2024-12-19 16:53:15 -06:00
Stephan Gerhold
d37e2646c8 arm64: dts: qcom: x1e80100-pmics: Enable all SMB2360 separately 
At the moment, x1e80100-pmics.dtsi enables two of the SMB2360 PMICs by
default and leaves the other two disabled. The third one was originally
also enabled by default, but then disabled in commit a237b8da41 ("arm64:
dts: qcom: x1e80100: Disable SMB2360_2 by default"). This is inconsistent
and confusing. Some laptops will even need SMB2360_1 disabled by default if
they just have a single USB-C port.

Make this consistent by keeping all SMB2360 disabled in x1e80100-pmics.dtsi
and enable them separately for all boards where needed. That way it is
always clear which ones are available and avoids accidentally trying to
read/write from missing chips when some of the PMICs are not present.

Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20241210-x1e80100-disable-smb2360-v2-1-2449be2eca29@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-16 14:30:51 -06:00
Jingyi Wang
45d55e2da9 arm64: dts: qcom: qcs8300: add base QCS8300 RIDE board 
Add initial support for Qualcomm QCS8300 RIDE board which enables DSPs,
UFS and booting to shell with uart console.

Written with help from Tingguo Cheng (added rpmhpd nodes) and Xin Liu
(added ufs, adsp and gpdsp nodes).

Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Link: https://lore.kernel.org/r/20241203-qcs8300_initial_dtsi-v4-4-d7c953484024@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-03 13:20:45 -06:00
Jingyi Wang
7be190e4bd arm64: dts: qcom: add QCS8300 platform 
Add initial DTSI for QCS8300 SoC.

Features added in this revision:
- CPUs with PSCI idle states
- Interrupt-controller with PDC wakeup support
- Timers, TCSR Clock Controllers
- Reserved Shared memory
- GCC and RPMHCC
- TLMM
- Interconnect
- QuP with uart
- SMMU
- QFPROM
- Rpmhpd power controller
- UFS
- Inter-Processor Communication Controller
- SRAM
- Remoteprocs including ADSP,CDSP and GPDSP
- BWMONs

Written with help from Zhenhua Huang(added the smmu node), Xin Liu(added
ufs, adsp and gpdsp nodes), Tingguo Cheng(added the rpmhpd node), Kyle
Deng(added the aoss_qmp node), Raviteja Laggyshetty(added interconnect
nodes) and Cong Zhang(added the INTID of EL2 non-secure physical timer).

Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Link: https://lore.kernel.org/r/20241203-qcs8300_initial_dtsi-v4-3-d7c953484024@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-03 13:20:19 -06:00
Jingyi Wang
d511280ce9 dt-bindings: arm: qcom: document QCS8300 SoC and reference board 
Document Qualcomm QCS8300 SoC and its reference board QCS8300 RIDE.

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Link: https://lore.kernel.org/r/20241203-qcs8300_initial_dtsi-v4-1-d7c953484024@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-03 13:20:19 -06:00
Krishna Kurapati
5c66811c92 arm64: dts: qcom: qcs615-ride: Enable primary USB interface 
Enable primary USB controller on QCS615 Ride platform. The primary USB
controller is made "peripheral", as this is intended to be connected to
a host for debugging use cases.

For using the controller in host mode, changing the dr_mode and adding
appropriate pinctrl nodes to provide vbus would be sufficient.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241121063007.2737908-3-quic_kriskura@quicinc.com
[bjorn: Fixed subject]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-01 22:29:55 -06:00
Krishna Kurapati
4b2769c7d7 arm64: dts: qcom: qcs615: Add primary USB interface 
Add support for primary USB controller and its PHYs on
QCS615.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241121063007.2737908-2-quic_kriskura@quicinc.com
[bjorn: Fixed subject]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-01 22:29:24 -06:00
Viken Dadhaniya
f6746dc9e3 arm64: dts: qcom: qcs615: Add QUPv3 configuration 
Add DT support for QUPv3 Serial Engines.

Co-developed-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>
Signed-off-by: Mukesh Kumar Savaliya <quic_msavaliy@quicinc.com>
Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com>
Link: https://lore.kernel.org/r/20241115101501.1995843-1-quic_vdadhani@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-01 22:26:00 -06:00
Jie Gan
bf46963055 arm64: dts: qcom: qcs615: Add coresight nodes 
Add following coresight components on QCS615, EUD, TMC/ETF, TPDM, dynamic
Funnel, TPDA, Replicator and ETM.

Signed-off-by: Jie Gan <quic_jiegan@quicinc.com>
Link: https://lore.kernel.org/r/20241106094510.2654998-1-quic_jiegan@quicinc.com
[bjorn: Fix patch subject]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-01 22:19:47 -06:00
Qingqing Zhou
58241be900 arm64: dts: qcom: qcs615: add the APPS SMMU node 
Add the APPS SMMU node for QCS615 platform. Add the dma-ranges
to limit DMA address range to 36bit width to align with system
architecture.

Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241105032107.9552-4-quic_qqzhou@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-01 22:19:47 -06:00
Qingqing Zhou
8c7f9d73de arm64: dts: qcom: qcs615: add the SCM node 
Add the SCM node for QCS615 platform. It is an interface to
communicate to the secure firmware.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Qingqing Zhou <quic_qqzhou@quicinc.com>
Link: https://lore.kernel.org/r/20241105032107.9552-3-quic_qqzhou@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-01 22:19:47 -06:00
Song Xue
29af58ab4d arm64: dts: qcom: qcs615: Add LLCC support for QCS615 
The QCS615 platform has LLCC(Last Level Cache Controller) as the system
cache controller. It includes 1 LLCC instance and 1 LLCC broadcast
interface.

Add LLCC node support for the QCS615 platform.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Song Xue <quic_songxue@quicinc.com>
Link: https://lore.kernel.org/r/20241031-add_llcc_dts_node_for_qcs615-v2-1-205766a607ca@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-01 22:19:47 -06:00