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Marijn Suijten
fa7ff6e9f1 arm64: dts: qcom: sm6125-seine: Lock eMMC and SD Card IDs via aliases 
Ensure the eMMC and SD Card always have a predictable slot index by
predetermining them via aliases.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222203636.250190-6-marijn.suijten@somainline.org
 2022-12-29 10:59:47 -06:00
Marijn Suijten
d696b1618b arm64: dts: qcom: sm6125-seine: Configure SD Card slot on SDHCI 2 
Sony's seine board features an SD Card slot on SDHCI 2, that is to be
powered by l5 and l22.  The card detect pin is already biased via
updates on the generic sdc2_*_state pinctrl nodes.

As usual regulator voltages are decreased to the maximum voted by the
downstream driver for safety.  SDHCI 2 is the only hardware block
feeding off of these.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222203636.250190-5-marijn.suijten@somainline.org
 2022-12-29 10:59:47 -06:00
Marijn Suijten
68aadbe780 arm64: dts: qcom: sm6125-seine: Provide regulators to SDHCI 1 
While SDHCI 1 appears to work out of the box, we cannot rely on the
bootloader-enabled regulators nor expect them to remain enabled (e.g.
when finally dropping pd_ignore_unused).  Provide it the necessary l24
and l11 regulators now that PM6125 regulators have been made available
on this board.

As usual regulator voltages are decreased to the maximum voted by the
downstream driver for safety.  No other hardware feeds off of these
regulators anyway (except UFS, which isn't used on the seine board in
favour of a DV6DMB eMMC card connected to SDHCI 1).

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222203636.250190-4-marijn.suijten@somainline.org
 2022-12-29 10:59:22 -06:00
Marijn Suijten
232bb8073b arm64: dts: qcom: sm6125-seine: Provide regulators to HS USB2 PHY 
Document the use of l7, l10 and l15 in the High Speed Qualcomm USB2 PHY,
in order to keep the regulators voted on when USB is active.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222203636.250190-3-marijn.suijten@somainline.org
 2022-12-29 10:59:22 -06:00
Marijn Suijten
7421a8d2f1 arm64: dts: qcom: sm6125-seine: Configure PM6125 regulators 
Configure PM6125 regulators based on availability and voltages defined
downstream, to allow powering up (and/or keeping powered) other hardware
blocks going forward.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222203636.250190-2-marijn.suijten@somainline.org
 2022-12-29 10:59:22 -06:00
Marijn Suijten
a40f5ae1ea arm64: dts: qcom: sm6350-lena: Flatten gpio-keys pinctrl state 
Pinctrl states typically collate multiple related pins.  In the case of
gpio-keys there's no hardware-defined relation at all except all pins
representing a key; and especially on Sony's lena board there's only one
pin regardless. Flatten it similar to other boards [1].

As a drive-by fix, clean up the label string.

[1]: https://lore.kernel.org/linux-arm-msm/11174eb6-0a9d-7df1-6f06-da4010f76453@linaro.org/

Fixes: 2b8bbe9856 ("arm64: dts: qcom: sm6350-lena: Include pm6350 and configure buttons")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222215906.324092-1-marijn.suijten@somainline.org
 2022-12-29 10:55:51 -06:00
Bryan O'Donoghue
ff114e399e arm64: dts: qcom: sm8250: Add compat qcom,sm8250-dsi-ctrl 
Add silicon specific compatible qcom,sm8250-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sm8250 against the yaml documentation.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223021025.1646636-19-bryan.odonoghue@linaro.org
 2022-12-29 10:55:23 -06:00
Bryan O'Donoghue
a1a685c312 arm64: dts: qcom: sdm845: Add compat qcom,sdm845-dsi-ctrl 
Add silicon specific compatible qcom,sdm845-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sdm845 against the yaml documentation.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223021025.1646636-18-bryan.odonoghue@linaro.org
 2022-12-29 10:55:23 -06:00
Bryan O'Donoghue
3381020a77 arm64: dts: qcom: sdm660: Add compat qcom,sdm660-dsi-ctrl 
Add silicon specific compatible qcom,sdm660-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sdm660 against the yaml documentation.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223021025.1646636-17-bryan.odonoghue@linaro.org
 2022-12-29 10:55:23 -06:00
Bryan O'Donoghue
197d28d463 arm64: dts: qcom: sdm630: Add compat qcom,sdm660-dsi-ctrl 
The sdm630 can use the sdm660 mdss-dsi-ctrl compat. Currently it has the
same set of binding dependencies as sdm660.

Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223021025.1646636-16-bryan.odonoghue@linaro.org
 2022-12-29 10:55:23 -06:00
Bryan O'Donoghue
5b5e4ac378 arm64: dts: qcom: sc7280: Add compat qcom,sc7280-dsi-ctrl 
Add silicon specific compatible qcom,sc7280-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sc7280 against the yaml documentation.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223021025.1646636-15-bryan.odonoghue@linaro.org
 2022-12-29 10:55:22 -06:00
Bryan O'Donoghue
a45d0641d1 arm64: dts: qcom: sc7180: Add compat qcom,sc7180-dsi-ctrl 
Add silicon specific compatible qcom,sc7180-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sc7180 against the yaml documentation.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223021025.1646636-14-bryan.odonoghue@linaro.org
 2022-12-29 10:55:22 -06:00
Bryan O'Donoghue
5ebe419128 arm64: dts: qcom: msm8996: Add compat qcom,msm8996-dsi-ctrl 
Add silicon specific compatible qcom,msm8996-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for msm8996 against the yaml documentation.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223021025.1646636-13-bryan.odonoghue@linaro.org
 2022-12-29 10:55:22 -06:00
Bryan O'Donoghue
634ecbc6b1 arm64: dts: qcom: msm8953: Add compat qcom,msm8953-dsi-ctrl 
Add silicon specific compatible qcom,msm8953-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for msm8953 against the yaml documentation.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223021025.1646636-12-bryan.odonoghue@linaro.org
 2022-12-29 10:55:22 -06:00
Bryan O'Donoghue
cd8cecc723 arm64: dts: qcom: msm8916: Add compat qcom,msm8916-dsi-ctrl 
Add silicon specific compatible qcom,msm8916-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for msm8916 against the yaml documentation.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223021025.1646636-11-bryan.odonoghue@linaro.org
 2022-12-29 10:55:22 -06:00
Krzysztof Kozlowski
06a0676b5d arm64: dts: qcom: sm8350: align MMC node names with DT schema 
The bindings expect "mmc" for MMC/SDHCI nodes:

  sm8350-sony-xperia-sagami-pdx214.dtb: sdhci@8804000: $nodename:0: 'sdhci@8804000' does not match '^mmc(@.*)?$'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223161835.112079-4-krzysztof.kozlowski@linaro.org
 2022-12-29 10:53:40 -06:00
Alex Elder
9472edb3e7 arm64: dts: qcom: sc7280: only enable IPA for boards with a modem 
IPA is only needed on a platform if it includes a modem, and not all
SC7280 SoC variants do.  The file "sc7280-herobrine-lte-sku.dtsi" is
used to encapsulate definitions related to Chrome OS SC7280 devices
where a modem is present, and that's the proper place for the IPA
node to be enabled.

Currently IPA is enabled in "sc7280-idp.dtsi", which is included by
DTS files for Qualcomm reference platforms (all of which include the
modem).  That also includes "sc7280-herobrine-lte-sku.dtsi", so
enabling IPA there would make it unnecessary for "sc7280-idp.dtsi"
to enable it.

The only other place IPA is enabled is "sc7280-qcard.dtsi".
That file is included only by "sc7280-herobrine.dtsi", which
is (eventually) included only by these top-level DTS files:
  sc7280-herobrine-crd.dts
  sc7280-herobrine-herobrine-r1.dts
  sc7280-herobrine-evoker.dts
  sc7280-herobrine-evoker-lte.dts
  sc7280-herobrine-villager-r0.dts
  sc7280-herobrine-villager-r1.dts
  sc7280-herobrine-villager-r1-lte.dts
All of but two of these include "sc7280-herobrine-lte-sku.dtsi", and
for those cases, enabling IPA there means there is no need for it to
be enabled in "sc7280-qcard.dtsi".

The two remaining cases will no longer enable IPA as a result of
this change:
  sc7280-herobrine-evoker.dts
  sc7280-herobrine-villager-r1.dts
Both of these have "lte" counterparts, and are meant to represent
board variants that do *not* have a modem.

This is exactly the desired configuration.

Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Tested-by: Sibi Sankar <quic_sibis@quicinc.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221224002126.1518552-1-elder@linaro.org
 2022-12-29 10:52:18 -06:00
Krzysztof Kozlowski
8ea261588f arm64: dts: qcom: sm8350-sony-xperia-sagami: specify which LDO modes are allowed 
This board uses RPMH, specifies "regulator-allow-set-load" for LDOs,
but doesn't specify any modes with "regulator-allowed-modes":

  sm8350-sony-xperia-sagami-pdx214.dtb: regulators-0: ldo5: 'regulator-allowed-modes' is a dependency of 'regulator-allow-set-load'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221228112456.31348-2-krzysztof.kozlowski@linaro.org
 2022-12-29 10:45:33 -06:00
Konrad Dybcio
98874a4668 arm64: dts: qcom: sm8150: Wire up MDSS 
Add required nodes for MDSS and hook up provided clocks in DISPCC.
This setup is almost identical to 8[23]50.

Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # Xperia 5
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229100511.979972-3-konrad.dybcio@linaro.org
 2022-12-29 10:39:43 -06:00
Konrad Dybcio
2ef3bb17c4 arm64: dts: qcom: sm8150: Add DISPCC node 
Years after the SoC support has been added, it's high time for it to
get dispcc going. Add the node to ensure that.

Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # Xperia 5
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229100511.979972-2-konrad.dybcio@linaro.org
 2022-12-29 10:39:43 -06:00
Krzysztof Kozlowski
ac1d8a8e2e arm64: dts: qcom: sm8250: add cache size 
Add full cache description to DTS to avoid:
1. "Early cacheinfo failed" warnings,
2. Cache topology detection which leads to early memory allocations and
   "BUG: sleeping function called from invalid context" on PREEMPT_RT
   kernel:

  smp: Bringing up secondary CPUs ...
  Detected VIPT I-cache on CPU1
  BUG: sleeping function called from invalid context at kernel/locking/spinlock_rt.c:46
  in_atomic(): 1, irqs_disabled(): 128, non_block: 0, pid: 0, name: swapper/1
  preempt_count: 1, expected: 0
  RCU nest depth: 1, expected: 1
  3 locks held by swapper/1/0:
   #0: ffff5e337eee5f18 (&pcp->lock){+.+.}-{3:3}, at: get_page_from_freelist+0x20c/0xffc
   #1: ffffa9e24a900b18 (rcu_read_lock){....}-{1:3}, at: rt_spin_trylock+0x40/0xe4
   #2: ffff5e337efc8918 (&zone->lock){+.+.}-{3:3}, at: rmqueue_bulk+0x54/0x720
  irq event stamp: 0
  Call trace:
   __might_resched+0x17c/0x214
   rt_spin_lock+0x5c/0x100
   rmqueue_bulk+0x54/0x720
   get_page_from_freelist+0xcfc/0xffc
   __alloc_pages+0xec/0x1150
   alloc_page_interleave+0x1c/0xd0
   alloc_pages+0xec/0x160
   new_slab+0x330/0x454
   ___slab_alloc+0x5b8/0xba0
   __kmem_cache_alloc_node+0xf4/0x20c
   __kmalloc+0x60/0x100
   detect_cache_attributes+0x2a8/0x5a0
   update_siblings_masks+0x28/0x300
   store_cpu_topology+0x58/0x70
   secondary_start_kernel+0xc8/0x154

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229132731.1193713-1-krzysztof.kozlowski@linaro.org
 2022-12-29 10:38:56 -06:00
Pierre Gondois
9435294c65 arm64: dts: qcom: Update cache properties 
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).

Update the Device Trees accordingly.

About msm8953.dtsi:
According to the Devicetree Specification v0.3,
s3.7.3 'Internal (L1) Cache Properties',
  cache-unified:
  If present, specifies the cache has a unified or-
  ganization. If not present, specifies that the
  cache has a Harvard architecture with separate
  caches for instructions and data.
Plus, the 'cache-level' property seems to be reserved to higher
cache levels (cf s3.8).

To describe a l1 data/instruction cache couple, no cache
information should be described. Remove the l1 cache nodes.

Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
[bjorn: Moved "qcom" to $subject prefix]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107155825.1644604-17-pierre.gondois@arm.com
 2022-12-29 10:22:11 -06:00
Konrad Dybcio
dcc7cd5c46 arm64: dts: qcom: sm8350-sagami: Rectify GPIO keys 
With enough pins set properly, the hardware buttons now also work
like a charm.

Fixes: c2721b0c23 ("arm64: dts: qcom: Add support for Xperia 1 III / 5 III")
Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # On Xperia 1 III and Xperia 5 III
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229102712.983306-1-konrad.dybcio@linaro.org
 2022-12-29 10:06:49 -06:00
Gabriela David
3176c4d6b9 arm64: dts: qcom: sdm632: Add device tree for Motorola G7 Power 
Add device tree for the Motorola G7 Power (ocean) smartphone. This
device is based on Snapdragon 632 (sdm632) SoC which is a variant of
MSM8953.

Signed-off-by: Gabriela David <ultracoolguy@disroot.org>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207-msm8953-6-1-next-dtbs-v3-v3-9-a64b3b0af0eb@z3ntu.xyz
 2022-12-28 21:36:45 -06:00
Eugene Lepshy
aa17e707e0 arm64: dts: qcom: msm8953: Add device tree for Xiaomi Redmi 5 Plus 
Add device tree for the Xiaomi Redmi 5 Plus (vince) smartphone. This
device is based on Snapdragon 625 (msm8953) SoC.

Signed-off-by: Eugene Lepshy <fekz115@gmail.com>
Co-developed-by: Gianluca Boiano <morf3089@gmail.com>
Signed-off-by: Gianluca Boiano <morf3089@gmail.com>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207-msm8953-6-1-next-dtbs-v3-v3-8-a64b3b0af0eb@z3ntu.xyz
 2022-12-28 21:36:45 -06:00
Danila Tikhonov
cf152c05eb arm64: dts: qcom: msm8953: Add device tree for Xiaomi Mi A1 
Add device tree for the Xiaomi Mi A1 (tissot) smartphone. This device is
based on Snapdragon 625 (msm8953) SoC.

Co-developed-by: Anton Bambura <jenneron@protonmail.com>
Signed-off-by: Anton Bambura <jenneron@protonmail.com>
Signed-off-by: Danila Tikhonov <JIaxyga@protonmail.com>
Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207-msm8953-6-1-next-dtbs-v3-v3-7-a64b3b0af0eb@z3ntu.xyz
 2022-12-28 21:36:45 -06:00
Adam Skladowski
c144005129 arm64: dts: qcom: msm8953: Add device tree for Xiaomi Redmi Note 4X 
Add device tree for the Xiaomi Redmi Note 4X (mido) smartphone. This
device is based on Snapdragon 625 (msm8953) SoC.

Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207-msm8953-6-1-next-dtbs-v3-v3-6-a64b3b0af0eb@z3ntu.xyz
 2022-12-28 21:36:45 -06:00
Alejandro Tafalla
38d779c263 arm64: dts: qcom: msm8953: Add device tree for Xiaomi Mi A2 Lite 
Add device tree for the Xiaomi Mi A2 Lite (daisy) smartphone. This
device is based on Snapdragon 625 (msm8953) SoC.

Signed-off-by: Alejandro Tafalla <atafalla@dnyon.com>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207-msm8953-6-1-next-dtbs-v3-v3-5-a64b3b0af0eb@z3ntu.xyz
 2022-12-28 21:36:45 -06:00
Sireesh Kodali
4ccd0dd6a3 arm64: dts: qcom: msm8953: Add device tree for Motorola G5 Plus 
Add device tree for the Motorola G5 Plus (potter) smartphone. This
device is based on Snapdragon 625 (msm8953) SoC.

Signed-off-by: Sireesh Kodali <sireeshkodali1@gmail.com>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207-msm8953-6-1-next-dtbs-v3-v3-4-a64b3b0af0eb@z3ntu.xyz
 2022-12-28 21:36:45 -06:00
Julian Braha
eee5a89b4f arm64: dts: qcom: sdm450: Add device tree for Motorola Moto G6 
Add device tree for the Motorola Moto G6 (ali) smartphone. This device
is based on Snapdragon 450 (sdm450) SoC which is a variant of MSM8953.

Signed-off-by: Julian Braha <julianbraha@gmail.com>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207-msm8953-6-1-next-dtbs-v3-v3-3-a64b3b0af0eb@z3ntu.xyz
 2022-12-28 21:36:45 -06:00
Luca Weiss
eca9ee35e8 arm64: dts: qcom: msm8953: Adjust reserved-memory nodes 
Adjust node names so they're not just memory@ but actually show what
they're used for. Also add labels to most nodes so we can easily
reference them from devices.

Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207-msm8953-6-1-next-dtbs-v3-v3-2-a64b3b0af0eb@z3ntu.xyz
 2022-12-28 21:36:45 -06:00
Dzmitry Sankouski
4c881ab73a arm64: dts: qcom: Re-enable resin on MSM8998 and SDM845 boards 
resin node declaration was moved to pm8998.dtsi file (in disabled state).
MSM8998 and SDM845 boards defining resin node did not previously have
status="okay" and ended up disabled.
Re-enable it by using resin node link from pm8998.dtsi with status="okay".

Fixes: f86ae6f23a ("arm64: dts: qcom: sagit: add initial device tree for sagit")
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reported-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/linux-arm-msm/20221222115922.jlachctn4lxopp7a@SoMainline.org/
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221228115243.201038-1-dsankouski@gmail.com
 2022-12-28 13:09:04 -06:00
Youghandhar Chintala
dc58c4d160 arm64: dts: qcom: sc7280: Add wifi alias for SC7280-idp 
Currently, depth-charge Chrome OS bootloader code used in the SC7280
SoC accesses the WiFi node using node names (wifi@<addr>). Since
depth-charge Chrome OS bootloader is a common code that is used in
SoCs having different WiFi chipsets, it is better if the depth-charge
Chrome OS bootloader code accesses the WiFi node using a WiFi alias.
The advantage of this method is that the depth-charge Chrome OS
bootloader code need not be changed for every new WiFi chip.
Therefore, add wifi alias entry for SC7280-idp device tree.

Signed-off-by: Youghandhar Chintala <quic_youghand@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221228094104.356-1-quic_youghand@quicinc.com
 2022-12-28 13:08:10 -06:00
Johan Hovold
3abf1f5c18 arm64: dts: qcom: sc8280xp-x13s: move 'regulator-vph-pwr' node 
Move the new 'regulator-vph-pwr' node before the wlan regulator node to
restore the root-node sort order (alphabetically by node name).

While at it, add a couple of newlines to separate the properties for
consistency with the other regulator nodes.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221228085614.15080-1-johan+linaro@kernel.org
 2022-12-28 13:07:57 -06:00
Steev Klimaszewski
40103eabe3 arm64: dts: qcom: c630: Fix firmware paths 
The firmware paths were pointing to qcom/manufacturer whereas other
devices have them under qcom/chipset/manufacturer, so fix this up on the
c630, so we follow the same standard setup.

Signed-off-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221226004727.204986-1-steev@kali.org
 2022-12-28 13:05:55 -06:00
Souradeep Chowdhury
91269c4256 arm64: dts: qcom: sdm845: Add Data Capture and Compare(DCC) support node 
Add the DCC(Data Capture and Compare) device tree node entry along with
the address of the register region.

Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/4b4289063e1b3baf98b653274060f35a5c888609.1672148732.git.quic_schowdhu@quicinc.com
 2022-12-28 11:24:34 -06:00
Souradeep Chowdhury
add74cad7c arm64: dts: qcom: sc7180: Add Data Capture and Compare(DCC) support node 
Add the DCC(Data Capture and Compare) device tree node entry along with
the address of the register region.

Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/08e8dc0f58145915f19d953c487a0df20a1ced1f.1672148732.git.quic_schowdhu@quicinc.com
 2022-12-28 11:24:34 -06:00
Souradeep Chowdhury
029d6586dc arm64: dts: qcom: sc7280: Add Data Capture and Compare(DCC) support node 
Add the DCC(Data Capture and Compare) device tree node entry along with
the address of the register region.

Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/88ef6053ee56eb0613040ea1fe33439934810330.1672148732.git.quic_schowdhu@quicinc.com
 2022-12-28 11:24:34 -06:00
Souradeep Chowdhury
d4b94c8244 arm64: dts: qcom: sm8150: Add Data Capture and Compare(DCC) support node 
Add the DCC(Data Capture and Compare) device tree node entry along with
the addresses for register regions.

Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/4737bcbce591e59b2f29d9141c1a5e41e64cc4f4.1672148732.git.quic_schowdhu@quicinc.com
 2022-12-28 11:24:34 -06:00
Marijn Suijten
c34bef62a0 arm64: dts: qcom: sm8150: Enable split pagetables for Adreno SMMU 
Allow the Adreno GPU to access split pagetables specifically on the
dedicated Adreno SMMU via the qcom,adreno-smmu compatible.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221213002626.260267-2-konrad.dybcio@linaro.org
 2022-12-28 11:10:51 -06:00
Vinod Koul
0f48b65f71 arm64: dts: qcom: sm8450-hdk: Enable HDMI Display 
Add the HDMI display nodes and link it to DSI.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207012803.114959-6-dmitry.baryshkov@linaro.org
 2022-12-28 10:54:40 -06:00
Vinod Koul
0cbe8e1953 arm64: dts: qcom: sm8450-hdk: Add LT9611uxc HDMI bridge 
Add the LT9611uxc DSI-HDMI bridge and supplies

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207012803.114959-5-dmitry.baryshkov@linaro.org
 2022-12-28 10:54:40 -06:00
Dmitry Baryshkov
928a7b4269 arm64: dts: qcom: sm8450-hdk: enable display hardware 
Enable MDSS/DPU/DSI0 on SM8450-HDK device.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207012803.114959-4-dmitry.baryshkov@linaro.org
 2022-12-28 10:54:39 -06:00
Dmitry Baryshkov
a6dd1206e4 arm64: dts: qcom: sm8450: add display hardware devices 
Add devices tree nodes describing display hardware on SM8450:
- Display Clock Controller
- MDSS
- MDP
- two DSI controllers and DSI PHYs

This does not provide support for DP controllers present on SM8450.

Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207012803.114959-3-dmitry.baryshkov@linaro.org
 2022-12-28 10:54:39 -06:00
Dmitry Baryshkov
a5ac24ba17 arm64: dts: qcom: sm8450: add RPMH_REGULATOR_LEVEL_LOW_SVS_D1 
Add another power saving state used on SM8450. Unfortunately adding it
in proper place causes renumbering of all the opp states in sm8450.dtsi

Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207012803.114959-2-dmitry.baryshkov@linaro.org
 2022-12-28 10:54:39 -06:00
Richard Acayan
861b67fbdc arm64: dts: qcom: sdm670-google-sargo: keep pm660 ldo8 on 
According to the downstream device tree, the regulator that powers the
I/O for eMMC should not be turned off. Keep it always on just in case
the eMMC driver fails and doesn't enable it, or unloads and disables it.

Fixes: 07c8ded6e3 ("arm64: dts: qcom: add sdm670 and pixel 3a device trees")
Link: 9ed6ddbe95/arch/arm64/boot/dts/google/sdm670-bonito-common.dtsi (105)
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221205225237.200564-1-mailingradian@gmail.com
 2022-12-28 10:50:27 -06:00
Johan Hovold
5e4cab734c arm64: dts: qcom: sc8280xp-x13s: move 'thermal-zones' node 
Move the 'thermal-zones' node after the regulator nodes to restore the
root-node sort order (alphabetically by node name).

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221227170202.21618-1-johan+linaro@kernel.org
 2022-12-27 22:35:22 -06:00
Konrad Dybcio
20e954411c arm64: dts: qcom: sdm845: Fix some whitespace/newlines 
Remove unnecessary newlines and fix up whitespace near the soundwire
controller node.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221212111037.98160-10-konrad.dybcio@linaro.org
 2022-12-27 22:21:57 -06:00
Konrad Dybcio
51f748c623 arm64: dts: qcom: sm8150: Use lowercase hex 
Use lowercase hex, as that's the preferred and overwhermingly present
style.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221212111037.98160-9-konrad.dybcio@linaro.org
 2022-12-27 22:21:57 -06:00
Konrad Dybcio
74f9165935 arm64: dts: qcom: sm8250: Use lowercase hex 
Use lowercase hex, as that's the preferred and overwhermingly present
style.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221212111037.98160-8-konrad.dybcio@linaro.org
 2022-12-27 22:21:57 -06:00