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Sean Anderson
f28cbab9bb pinctrl: zynqmp: Support muxing individual pins 
While muxing groups of pins at once can be convenient for large
interfaces, it can also be rigid. This is because the group is set to
all pins which support a particular function, even though not all pins
may be used. For example, the sdhci0 function may be used with a 8-bit
eMMC, 4-bit SD card, or even a 1-bit SD card. In these cases, the extra
pins may be repurposed for other uses, but this is not currently
allowed.

There is not too much point in pin "groups" when there are not actual
pin groups at the hardware level. The pins can all be muxed
individually, so there's no point in adding artificial groups on top.
Just mux the pins like the hardware allows.

To this effect, add a new group for each pin which can be muxed. These
groups are part of each function the pin can be muxed to. We treat group
selectors beyond the number of groups as "pin" groups. To set this up,
we initialize groups before functions, and then create a bitmap of used
pins for each function. These used pins are appended to the function's
list of groups.

Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Reviewed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Acked-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240610223550.2449230-3-sean.anderson@linux.dev
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 10:47:06 +02:00
Sean Anderson
58ba921150 dt-bindings: pinctrl: xilinx: Add support for function with pins 
Support specifying the function per-pin. The driver doesn't care
whether you use pins or groups for this purpose.

Signed-off-by: Sean Anderson <sean.anderson@linux.dev>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Acked-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20240610223550.2449230-2-sean.anderson@linux.dev
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 10:47:06 +02:00
Yang Yingliang
9b401f4a71 pinctrl: ti: ti-iodelay: fix possible memory leak when pinctrl_enable() fails 
This driver calls pinctrl_register_and_init() which is not
devm_ managed, it will leads memory leak if pinctrl_enable()
fails. Replace it with devm_pinctrl_register_and_init().
And add missing of_node_put() in the error path.

Fixes: 5038a66dad ("pinctrl: core: delete incorrect free in pinctrl_enable()")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org>
Link: https://lore.kernel.org/r/20240606023704.3931561-4-yangyingliang@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 10:33:30 +02:00
Yang Yingliang
8f773bfbdd pinctrl: single: fix possible memory leak when pinctrl_enable() fails 
This driver calls pinctrl_register_and_init() which is not
devm_ managed, it will leads memory leak if pinctrl_enable()
fails. Replace it with devm_pinctrl_register_and_init().
And call pcs_free_resources() if pinctrl_enable() fails.

Fixes: 5038a66dad ("pinctrl: core: delete incorrect free in pinctrl_enable()")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org>
Link: https://lore.kernel.org/r/20240606023704.3931561-3-yangyingliang@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 10:33:30 +02:00
Yang Yingliang
ae1cf47599 pinctrl: core: fix possible memory leak when pinctrl_enable() fails 
In devm_pinctrl_register(), if pinctrl_enable() fails in pinctrl_register(),
the "pctldev" has not been added to dev resources, so devm_pinctrl_dev_release()
can not be called, it leads memory leak.

Introduce pinctrl_uninit_controller(), call it in the error path to free memory.

Fixes: 5038a66dad ("pinctrl: core: delete incorrect free in pinctrl_enable()")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Dan Carpenter <dan.carpenter@linaro.org>
Link: https://lore.kernel.org/r/20240606023704.3931561-2-yangyingliang@huawei.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 10:33:30 +02:00
Stefan Wahren
1583dc1627 pinctrl: bcm2835: Use string_choices API instead of ternary operator 
Use modern string_choices API instead of manually determining the
output using ternary operator.

Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Acked-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://lore.kernel.org/r/20240603181938.76047-3-wahrenst@gmx.net
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:50:11 +02:00
Andrew Jeffery
1d1f3b8490 dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Describe I3C, USB 
I3C1 and I3C2 become muxed functions in the mass production release of
the AST2600. Also document the USB2A device and USB2B HID mux options.

Squash warnings such as:

    arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-elbert.dtb: pinctrl: usb2ad_default:function:0: 'USB2AD' is not one of ['ADC0', 'ADC1', 'ADC10', 'ADC11', 'ADC12', 'ADC13', 'ADC14', 'ADC15', 'ADC2', 'ADC3', 'ADC4', 'ADC5', 'ADC6', 'ADC7', 'ADC8', 'ADC9', 'BMCINT', 'EMMC', 'ESPI', 'ESPIALT', 'FSI1', 'FSI2', 'FWQSPI', 'FWSPIABR', 'FWSPID', 'FWSPIWP', 'GPIT0', 'GPIT1', 'GPIT2', 'GPIT3', 'GPIT4', 'GPIT5', 'GPIT6', 'GPIT7', 'GPIU0', 'GPIU1', 'GPIU2', 'GPIU3', 'GPIU4', 'GPIU5', 'GPIU6', 'GPIU7', 'I2C1', 'I2C10', 'I2C11', 'I2C12', 'I2C13', 'I2C14', 'I2C15', 'I2C16', 'I2C2', 'I2C3', 'I2C4', 'I2C5', 'I2C6', 'I2C7', 'I2C8', 'I2C9', 'I3C3', 'I3C4', 'I3C5', 'I3C6', 'JTAGM', 'LHPD', 'LHSIRQ', 'LPC', 'LPCHC', 'LPCPD', 'LPCPME', 'LPCSMI', 'LSIRQ', 'MACLINK1', 'MACLINK2', 'MACLINK3', 'MACLINK4', 'MDIO1', 'MDIO2', 'MDIO3', 'MDIO4', 'NCTS1', 'NCTS2', 'NCTS3', 'NCTS4', 'NDCD1', 'NDCD2', 'NDCD3', 'NDCD4', 'NDSR1', 'NDSR2', 'NDSR3', 'NDSR4', 'NDTR1', 'NDTR2', 'NDTR3', 'NDTR4', 'NRI1', 'NRI2', 'NRI3', 'NR
 I4', 'NRTS1', 'NRTS2', 'NRTS3', 'NRTS4', 'OSCCLK', 'PEWAKE', 'PWM0', 'PWM1', 'PWM10', 'PWM11', 'PWM12', 'PWM13', 'PWM14', 'PWM15', 'PWM2', 'PWM3', 'PWM4', 'PWM5', 'PWM6', 'PWM7', 'PWM8', 'PWM9', 'RGMII1', 'RGMII2', 'RGMII3', 'RGMII4', 'RMII1', 'RMII2', 'RMII3', 'RMII4', 'RXD1', 'RXD2', 'RXD3', 'RXD4', 'SALT1', 'SALT10', 'SALT11', 'SALT12', 'SALT13', 'SALT14', 'SALT15', 'SALT16', 'SALT2', 'SALT3', 'SALT4', 'SALT5', 'SALT6', 'SALT7', 'SALT8', 'SALT9', 'SD1', 'SD2', 'SGPM1', 'SGPM2', 'SGPS1', 'SGPS2', 'SIOONCTRL', 'SIOPBI', 'SIOPBO', 'SIOPWREQ', 'SIOPWRGD', 'SIOS3', 'SIOS5', 'SIOSCI', 'SPI1', 'SPI1ABR', 'SPI1CS1', 'SPI1WP', 'SPI2', 'SPI2CS1', 'SPI2CS2', 'TACH0', 'TACH1', 'TACH10', 'TACH11', 'TACH12', 'TACH13', 'TACH14', 'TACH15', 'TACH2', 'TACH3', 'TACH4', 'TACH5', 'TACH6', 'TACH7', 'TACH8', 'TACH9', 'THRU0', 'THRU1', 'THRU2', 'THRU3', 'TXD1', 'TXD2', 'TXD3', 'TXD4', 'UART10', 'UART11', 'UART12', 'UART13', 'UART6', 'UART7', 'UART8', 'UART9', 'USBAD', 'USBADP', 'USB2AH', 'USB2AHP', 'USB
 2BD', 'USB2BH', 'VB', 'VGAHS', 'VGAVS', 'WDTRST1', 'WDTRST2', 'WDTRST3', 'WDTRST4']

Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240531-dt-warnings-gpio-ast2600-pinctrl-funcs-groups-v1-3-a6fe2281a1b8@codeconstruct.com.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:33:51 +02:00
Andrew Jeffery
757d04a473 dt-bindings: pinctrl: aspeed,ast2500-pinctrl: Describe SGPM 
Squash warnings such as:

    arch/arm/boot/dts/aspeed/aspeed-ast2500-evb.dtb: pinctrl@80: sgpm_default:groups:0: 'SGPM' is not one of ['ACPI', 'ADC0', 'ADC1', 'ADC10', 'ADC11', 'ADC12', 'ADC13', 'ADC14', 'ADC15', 'ADC2', 'ADC3', 'ADC4', 'ADC5', 'ADC6', 'ADC7', 'ADC8', 'ADC9', 'BMCINT', 'DDCCLK', 'DDCDAT', 'ESPI', 'FWSPICS1', 'FWSPICS2', 'GPID0', 'GPID2', 'GPID4', 'GPID6', 'GPIE0', 'GPIE2', 'GPIE4', 'GPIE6', 'I2C10', 'I2C11', 'I2C12', 'I2C13', 'I2C14', 'I2C3', 'I2C4', 'I2C5', 'I2C6', 'I2C7', 'I2C8', 'I2C9', 'LAD0', 'LAD1', 'LAD2', 'LAD3', 'LCLK', 'LFRAME', 'LPCHC', 'LPCPD', 'LPCPLUS', 'LPCPME', 'LPCRST', 'LPCSMI', 'LSIRQ', 'MAC1LINK', 'MAC2LINK', 'MDIO1', 'MDIO2', 'NCTS1', 'NCTS2', 'NCTS3', 'NCTS4', 'NDCD1', 'NDCD2', 'NDCD3', 'NDCD4', 'NDSR1', 'NDSR2', 'NDSR3', 'NDSR4', 'NDTR1', 'NDTR2', 'NDTR3', 'NDTR4', 'NRI1', 'NRI2', 'NRI3', 'NRI4', 'NRTS1', 'NRTS2', 'NRTS3', 'NRTS4', 'OSCCLK', 'PEWAKE', 'PNOR', 'PWM0', 'PWM1', 'PWM2', 'PWM3', 'PWM4', 'PWM5', 'PWM6', 'PWM7', 'RGMII1', 'RGMII2', 'RMII1', 'RMII2', 'RXD1', '
 RXD2', 'RXD3', 'RXD4', 'SALT1', 'SALT10', 'SALT11', 'SALT12', 'SALT13', 'SALT14', 'SALT2', 'SALT3', 'SALT4', 'SALT5', 'SALT6', 'SALT7', 'SALT8', 'SALT9', 'SCL1', 'SCL2', 'SD1', 'SD2', 'SDA1', 'SDA2', 'SGPS1', 'SGPS2', 'SIOONCTRL', 'SIOPBI', 'SIOPBO', 'SIOPWREQ', 'SIOPWRGD', 'SIOS3', 'SIOS5', 'SIOSCI', 'SPI1', 'SPI1CS1', 'SPI1DEBUG', 'SPI1PASSTHRU', 'SPI2CK', 'SPI2CS0', 'SPI2CS1', 'SPI2MISO', 'SPI2MOSI', 'TIMER3', 'TIMER4', 'TIMER5', 'TIMER6', 'TIMER7', 'TIMER8', 'TXD1', 'TXD2', 'TXD3', 'TXD4', 'UART6', 'USB11BHID', 'USB2AD', 'USB2AH', 'USB2BD', 'USB2BH', 'USBCKI', 'VGABIOSROM', 'VGAHS', 'VGAVS', 'VPI24', 'VPO', 'WDTRST1', 'WDTRST2']

Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240531-dt-warnings-gpio-ast2600-pinctrl-funcs-groups-v1-2-a6fe2281a1b8@codeconstruct.com.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:33:51 +02:00
Andrew Jeffery
ed4db42976 dt-bindings: pinctrl: aspeed: Use block syntax for function and groups 
The expansion makes the documents a lot longer, but it's easier to
review changes to functions and groups when we're not having to deal
with line wrapping.

Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240531-dt-warnings-gpio-ast2600-pinctrl-funcs-groups-v1-1-a6fe2281a1b8@codeconstruct.com.au
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:33:51 +02:00
Linus Walleij
2659f36a56 Merge tag 'renesas-pinctrl-for-v6.11-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel 
pinctrl: renesas: Updates for v6.11

  - Add support for the new RZ/V2H(P) (R9A09G057) Soc,
  - Miscellaneous fixes and improvements.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:27:36 +02:00
Nathan Chancellor
c47d254117 pinctrl: keembay: Fix func conversion in keembay_build_functions() 
A recent refactoring to use the func member in struct function_desc
missed converting one uses of name in keembay_build_functions(),
resulting in a build failure:

  drivers/pinctrl/pinctrl-keembay.c: In function 'keembay_build_functions':
  drivers/pinctrl/pinctrl-keembay.c:1630:35: error: 'struct function_desc' has no member named 'name'
   1630 |                         if (!fdesc->name) {
        |                                   ^~

Perform the same conversion to resolve the build error.

Fixes: 73ee52205e5a ("pinctrl: keembay: Convert to use func member")
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Link: https://lore.kernel.org/r/20240611-pinctrl-keembay-fix-func-conversion-v1-1-3197f2ded3f7@kernel.org
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202406131133.WwdetfBL-lkp@intel.com/
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:26:28 +02:00
Peng Fan
b755521fd6 pinctrl: imx: support SCMI pinctrl protocol for i.MX95 
The generic pinctrl-scmi.c driver could not be used for i.MX95 because
i.MX95 SCMI firmware not supports functions, groups or generic
'Pin Configuration Type and Enumerations' listed in SCMI Specification.

i.MX95 System Control Management Interface(SCMI) firmware only supports
below pin configuration types which are OEM specific types:
    192: PIN MUX
    193: PIN CONF
    194: DAISY ID
    195: DAISY VAL

To Support fsl,pins property together with SCMI OEM protocol, add this
driver.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Cristian Marussi <cristian.marussi@arm.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Link: https://lore.kernel.org/r/20240521-pinctrl-scmi-imx95-v1-3-9a1175d735fd@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:26:18 +02:00
Peng Fan
dbd47012a4 pinctrl: scmi: add blocklist 
i.MX95 will have its own pinctrl scmi driver, so need block
pinctrl-scmi driver for i.MX95, otherwise there will be two pinctrl
devices for a single scmi protocol@19.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Link: https://lore.kernel.org/r/20240521-pinctrl-scmi-imx95-v1-2-9a1175d735fd@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:26:04 +02:00
Peng Fan
997f2cdea3 dt-bindings: firmware: arm,scmi: Add properties for i.MX95 Pinctrl OEM extensions 
i.MX95 Pinctrl is managed by System Control Management Interface(SCMI)
firmware using OEM extensions. No functions, no groups are provided by
the firmware. So add i.MX95 specific properties.

To keep aligned with current i.MX pinctrl bindings, still use "fsl,pins"
for i.MX95.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Link: https://lore.kernel.org/r/20240521-pinctrl-scmi-imx95-v1-1-9a1175d735fd@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:25:55 +02:00
Richard Acayan
d85e2ccdf1 pinctrl: qcom: sdm670: add pdc wakeirq map 
The PDC was hooked up as a wakeup parent in the DTS in
commit 71f080633d ("arm64: dts: qcom: sdm670: Hook up PDC as
wakeup-parent of TLMM"), but the wakeirq mapping was not defined so it
had no effect. Add the mapping for wakeup interrupts on the PDC to their
corresponding pins.

Configuring a pin IRQ as dual-edge would break it unless the
wakeirq_dual_edge_errata flag is set.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Link: https://lore.kernel.org/r/20240523230619.256882-2-mailingradian@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:25:45 +02:00
Patrick Rudolph
7f53a8eeb5 pinctrl: cy8c95x0: Use REGCACHE_MAPLE 
Use REGCACHE_MAPLE instead of REGCACHE_FLAT.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Link: https://lore.kernel.org/r/20240521152602.1097764-3-patrick.rudolph@9elements.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:25:37 +02:00
Patrick Rudolph
8670de9fae pinctrl: cy8c95x0: Use regmap ranges 
Instead of implementing a custom register paging mechanism in
the driver use the existing regmap ranges feature.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Link: https://lore.kernel.org/r/20240521152602.1097764-2-patrick.rudolph@9elements.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:25:27 +02:00
Patrick Rudolph
f71aba339a pinctrl: cy8c95x0: Use single I2C lock 
Currently there are 3 locks being used when accessing the chip, one
in the driver and one in each regmap. Reduce that to one driver only
lock that protects all regmap and regcache accesses.

Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Andy Shevchenko <andy@kernel.org>
Link: https://lore.kernel.org/r/20240521152602.1097764-1-patrick.rudolph@9elements.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:25:19 +02:00
Andy Shevchenko
c501b780c1 pinctrl: pinmux: Remove unused members from struct function_desc 
All drivers are converted to use embedded struct pinfunction.
Remove unused members from struct function_desc.

Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20240530085745.1539925-12-andy.shevchenko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:25:11 +02:00
Andy Shevchenko
6273a1b1ce pinctrl: mediatek: moore: Convert to use func member 
Convert drivers to use func member embedded in struct function_desc,
because other members will be removed to avoid duplication and
desynchronisation of the generic pin function description.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20240530085745.1539925-11-andy.shevchenko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:24:57 +02:00
Andy Shevchenko
ab8866c5d3 pinctrl: keembay: Convert to use func member 
Convert drivers to use func member embedded in struct function_desc,
because other members will be removed to avoid duplication and
desynchronisation of the generic pin function description.

Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20240530085745.1539925-10-andy.shevchenko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:24:49 +02:00
Andy Shevchenko
be9e92afd3 pinctrl: ingenic: Convert to use func member 
Convert drivers to use func member embedded in struct function_desc,
because other members will be removed to avoid duplication and
desynchronisation of the generic pin function description.

Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20240530085745.1539925-9-andy.shevchenko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:24:42 +02:00
Andy Shevchenko
f3e0473aa8 pinctrl: imx: Convert to use func member 
Convert drivers to use func member embedded in struct function_desc,
because other members will be removed to avoid duplication and
desynchronisation of the generic pin function description.

Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20240530085745.1539925-8-andy.shevchenko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:24:30 +02:00
Andy Shevchenko
37997d7b55 pinctrl: pinmux: Embed struct pinfunction into struct function_desc 
struct function_desc is a particular version of the struct pinfunction
with associated opaque data. Start switching pin control core and
drivers to use it explicitly.

Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20240530085745.1539925-7-andy.shevchenko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:24:22 +02:00
Andy Shevchenko
f26945d76a pinctrl: pinmux: Add a convenient define PINCTRL_FUNCTION_DESC() 
Add PINCTRL_FUNCTION_DESC() macro for inline use.

While at it, fix adjective form in the comment of PINCTRL_GROUP_DESC().

Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20240530085745.1539925-6-andy.shevchenko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:24:13 +02:00
Andy Shevchenko
dc02d925dc pinctrl: mediatek: moore: Provide a helper macro PINCTRL_PIN_FUNCTION() 
Provide a helper macro to assign the struct function_desc entries.
This helps further refactoring.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20240530085745.1539925-5-andy.shevchenko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:24:05 +02:00
Andy Shevchenko
7f2a2af088 pinctrl: ingenic: Provide a helper macro INGENIC_PIN_FUNCTION() 
Provide a helper macro to assign the struct function_desc entries.
This helps further refactoring.

Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20240530085745.1539925-4-andy.shevchenko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:23:56 +02:00
Andy Shevchenko
18f5c202de pinctrl: equilibrium: Make use of struct pinfunction 
Since pin control provides a generic data type for the pin function,
use it in the driver.

Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20240530085745.1539925-3-andy.shevchenko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:23:43 +02:00
Andy Shevchenko
5d421ff557 pinctrl: berlin: Make use of struct pinfunction 
Since pin control provides a generic data type for the pin function,
use it in the driver.

Signed-off-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20240530085745.1539925-2-andy.shevchenko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:23:34 +02:00
Dmitry Yashin
a8f2548548 pinctrl: rockchip: update rk3308 iomux routes 
Some of the rk3308 iomux routes in rk3308_mux_route_data belong to
the rk3308b SoC. Remove them and correct i2c3 routes.

Fixes: 7825aeb7b2 ("pinctrl: rockchip: add rk3308 SoC support")
Signed-off-by: Dmitry Yashin <dmt.yashin@gmail.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20240515121634.23945-2-dmt.yashin@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:23:26 +02:00
Swati Agarwal
5028736781 pinctrl: pinctrl-zynqmp: Use pin numbers stored in pin descriptor 
Use pin numbers stored in the pin descriptors instead of index value while
creating the pin groups. Pin Id's are not same as Index values for Xilinx
Versal platform, so use the pin values from descriptor which works for both
ZynqMP and Versal platforms.

Signed-off-by: Swati Agarwal <swati.agarwal@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/2413a1f99278d70313960f13daecda9ef54172d8.1716807432.git.michal.simek@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:23:18 +02:00
Weihao Li
0a2bcac1a2 pinctrl: ralink: mt76x8: fix pinmux function 
The current version of the pinctrl driver has some issues:

1. Duplicated "gpio" pmx function

The common code will add a "gpio" pmx functon to every pin group, so
it's not necessary to define a separate "gpio" pmx function in pin
groups.

2. Duplicated pmx function name

There are some same function name in different pin groups, which will
cause some problems. For example, when we want to use PAD_GPIO0 as
refclk output function, the common clk framework code will search the
entire pin function lists, then return the first one matched, in this
case the matched function list only include the PAD_CO_CLKO pin group
because there are three "refclk" pin function, which is added by
refclk_grp, spi_cs1_grp and gpio_grp.

To solve this problem, a simple way is just add a pingrp refix to
function name like mt7620 pinctrl driver does.

3. Useless "-" or "rsvd" functon

It's really unnecessary to add a reserved pin mux function to the
function lists, because we never use it.

Signed-off-by: Weihao Li <cn.liweihao@gmail.com>
Link: https://lore.kernel.org/r/20240527022036.31985-1-user@blabla
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:23:02 +02:00
Nirmala Devi Mal Nadar
72636eb9c1 pinctrl: pinctrl-tps6594: make tps65224_muxval_remap and tps6594_muxval_remap as static to fix sparse warning 
pinctrl: tps6594: Fix sparse warning.

warning: symbol 'tps65224_muxval_remap' was not declared. Should it be static?
warning: symbol 'tps6594_muxval_remap' was not declared. Should it be static?

Signed-off-by: Nirmala Devi Mal Nadar <m.nirmaladevi@ltts.com>
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202405111523.9yt759uX-lkp@intel.com/
Link: https://lore.kernel.org/r/0109018f85002ae1-6fb831b2-74c2-4559-98f1-a3ef25e72558-000000@ap-south-1.amazonses.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:22:49 +02:00
Konrad Dybcio
db43edf669 pinctrl: qcom: spmi: Add PMC8380 
PMC8380 is a new chip, featuring 10 GPIOs. Describe it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240525-topic-pmc8380_gpio-v2-2-2de50cb28ac1@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:22:41 +02:00
Konrad Dybcio
55f5d36e84 dt-bindings: pinctrl: qcom,pmic-gpio: Document PMC8380 
PMC8380 is a new PMIC used with X1 SoCs. Document it

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240525-topic-pmc8380_gpio-v2-1-2de50cb28ac1@linaro.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:22:33 +02:00
Léo DUBOIN
9dfbcf2fc5 pinctrl: core: reset gpio_device in loop in pinctrl_pins_show() 
We were not resetting the pointer to the associated gpio_device once
we are done displaying a pin's information.

This meant that once we reached the end of a gpio-range, if there
were pins right after it that did not belong to any known range,
they would be associated with the previous range's gpio device.

This resulted in those pins appearing as <4294966783:old_gdev> instead
of the expected <0:?> (due to gpio_num being -1).

Signed-off-by: Léo DUBOIN <lduboin@freebox.fr>
Link: https://lore.kernel.org/r/c40d0634abefa19e689ffd450e0f48a8d63c4fc4.1714049455.git.lduboin@freebox.fr
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:22:24 +02:00
Léo DUBOIN
db5032981a pinctrl: core: take into account the pins array in pinctrl_pins_show() 
We previously only looked at the 'pin_base' of the pinctrl_gpio_ranges
struct for determining if a pin matched a GPIO number.

This value is present only if the 'pins' array is not NULL,
and is 0 otherwise. This means that GPIO ranges declared using
gpiochip_add_pingroup_range(), thus making use of pins, were always matched
by the pins in the range [0-npins] even if they contained pins in a
completely separate range.

Signed-off-by: Léo DUBOIN <lduboin@freebox.fr>
Link: https://lore.kernel.org/r/6df39bd47942156be5713f8f4e317d2ad3e0ddeb.1714049455.git.lduboin@freebox.fr
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:22:15 +02:00
Jacky Huang
f805e35631 pinctrl: nuvoton: Add ma35d1 pinctrl and GPIO driver 
Add common pinctrl and GPIO driver for Nuvoton MA35 series SoC, and
add support for ma35d1 pinctrl.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
Link: https://lore.kernel.org/r/20240521012447.42211-4-ychuang570808@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:22:03 +02:00
Jacky Huang
63f1f9da45 dt-bindings: pinctrl: Document nuvoton ma35d1 pin control 
Add documentation to describe nuvoton ma35d1 pin control and GPIO.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240521012447.42211-3-ychuang570808@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:21:55 +02:00
Jacky Huang
c64c4b6882 dt-bindings: reset: Add syscon to nuvoton ma35d1 system-management node 
Add a compatible 'syscon' to the system management node since the system
control registers are mapped by this driver. The other driver must access
the system control registers through 'regmap' using a phandle that
references this node.

Signed-off-by: Jacky Huang <ychuang3@nuvoton.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20240521012447.42211-2-ychuang570808@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:21:46 +02:00
Peng Fan
b7141b18bf pinctrl: st: Use scope based of_node_put() cleanups 
Use scope based of_node_put() cleanup to simplify code.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20240504-pinctrl-cleanup-v2-8-26c5f2dc1181@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:21:38 +02:00
Peng Fan
2dbcd12d9e pinctrl: stm32: Use scope based of_node_put() cleanups 
Use scope based of_node_put() cleanup to simplify code.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Link: https://lore.kernel.org/r/20240504-pinctrl-cleanup-v2-3-26c5f2dc1181@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:21:32 +02:00
Peng Fan
993e2fc48f pinctrl: imx: Add pinctrl driver support for i.MX91 
Add NXP i.MX91 pinctrl driver

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20240513-imx91-pinctrl-v1-2-c99a23c6843a@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:21:21 +02:00
Peng Fan
1435dc1f39 dt-bindings: pinctrl: imx: Support i.MX91 IOMUXC 
i.MX91 and i.MX93 share similar design. They could share same dt-binding
doc, so rename fsl,imx93-pinctrl.yaml to fsl,imx9-pinctrl.yaml and add
i.MX91 compatible string

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240513-imx91-pinctrl-v1-1-c99a23c6843a@nxp.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2024-06-17 09:21:11 +02:00
Lad Prabhakar
9bd95ac86e pinctrl: renesas: rzg2l: Add support for RZ/V2H SoC 
Add pinctrl driver support for RZ/V2H(P) SoC.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240530173857.164073-16-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-06-11 09:50:25 +02:00
Lad Prabhakar
fb73d663b3 dt-bindings: pinctrl: renesas: Document RZ/V2H(P) SoC 
Add documentation for the pin controller found on the Renesas RZ/V2H(P)
(R9A09G057) SoC.  The RZ/V2H PFC varies slightly compared to the RZ/G2L
family:
  - Additional bits need to be set during pinmuxing,
  - The GPIO pin count is different.

Hence, a SoC-specific compatible string, 'renesas,r9a09g057-pinctrl', is
added for the RZ/V2H(P) SoC.

Also, add the 'renesas,output-impedance' property.  The drive strength
settings on RZ/V2H(P) depend on the different power rails coming out from
the PMIC (connected via I2C).  These power rails (required for drive
strength) can be 1.2V, 1.8V, or 3.3V.

Pins are grouped into 4 groups:

Group 1: Impedance
  - 150/75/38/25 ohms (at 3.3V)
  - 130/65/33/22 ohms (at 1.8V)

Group 2: Impedance
  - 50/40/33/25 ohms (at 1.8V)

Group 3: Impedance
  - 150/75/37.5/25 ohms (at 3.3V)
  - 130/65/33/22 ohms (at 1.8V)

Group 4: Impedance
  - 110/55/30/20 ohms (at 1.8V)
  - 150/75/38/25 ohms (at 1.2V)

The 'renesas,output-impedance' property, as documented, can be
[0, 1, 2, 3], these correspond to register bit values that can
be set in the PFC_IOLH_mn register, which adjusts the drive
strength value and is pin-dependent.

As power rail information may not be available very early in the boot
process, the 'renesas,output-impedance' property is added instead of
reusing the 'output-impedance-ohms' property.

Also, allow bias-disable, bias-pull-down and bias-pull-up properties
as these can be used to configure the pins.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240606085133.632307-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-06-11 09:50:25 +02:00
Lad Prabhakar
951eaac107 pinctrl: renesas: rzg2l: Acquire lock in rzg2l_pinctrl_pm_setup_pfc() 
To keep consistency with rzg2l_pinctrl_set_pfc_mode(), acquire the lock
in rzg2l_pinctrl_pm_setup_pfc() during PFC setup.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-15-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-06-11 09:50:24 +02:00
Lad Prabhakar
d930e8f783 pinctrl: renesas: rzg2l: Add support for custom parameters 
In preparation for passing custom params for RZ/V2H(P) SoC assign the
custom params that are being passed via struct rzg2l_pinctrl_data.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240530173857.164073-14-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-06-11 09:50:24 +02:00
Lad Prabhakar
6f38a02ad8 pinctrl: renesas: rzg2l: Pass pincontrol device to pinconf_generic_parse_dt_config() 
Pass the pincontrol device pointer to pinconf_generic_parse_dt_config()
in preparation for passing custom params.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> # on RZ/G3S
Link: https://lore.kernel.org/r/20240530173857.164073-13-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-06-11 09:50:24 +02:00
Lad Prabhakar
19d4bce9ce pinctrl: renesas: rzg2l: Add support for pull-up/down 
Add support to configure bias-disable, bias-pull-up, and bias-pull-down
properties of the pin.

Two new function pointers, hw_to_bias_param() and bias_param_to_hw(),
are introduced in the struct rzg2l_pinctrl_data to configure bias
settings, as the values in the PUPD register differ when compared to the
RZ/G2L family and the RZ/V2H(P) SoC.

Value | RZ/G2L        | RZ/V2H
---------------------------------
00b:  | Bias Disabled | Pull up/down disabled
01b:  | Pull-up       | Pull up/down disabled
10b:  | Pull-down     | Pull-down
11b:  | Prohibited    | Pull-up

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240530173857.164073-12-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-06-11 09:50:24 +02:00