mirrors/linux
2
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-13 19:59:34 -04:00
Code Issues Packages Projects Releases Wiki Activity
1,294,601 Commits 1 Branch 930 Tags
ecbdce2041ee09cb3a046fd2b7d000fa5e333773
Commit Graph

1294601 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Konrad Dybcio
ecbdce2041 arm64: dts: qcom: x1e80100: Add UART2 
GENI SE2 within QUP0 is used as UART on some devices, describe it.
While at it, rewrite the adjacent UART21 pins node to make it more
easily modifiable.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Link: https://lore.kernel.org/r/20240826-topic-sl7-v2-4-c32ebae78789@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-26 11:29:29 -05:00
Konrad Dybcio
02a1bfb34c arm64: dts: qcom: x1e80100-pmics: Add PMC8380C PWM 
The PMC8380C (PM8550) has a PWM block, describe it.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Link: https://lore.kernel.org/r/20240826-topic-sl7-v2-3-c32ebae78789@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-26 11:29:29 -05:00
Konrad Dybcio
2538d0689c dt-bindings: arm: qcom: Add Surface Laptop 7 devices 
Document the X1E80100-based Microsoft laptops.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240826-topic-sl7-v2-1-c32ebae78789@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-26 11:29:29 -05:00
Krzysztof Kozlowski
cad5b06c1f arm64: dts: qcom: sm8150-mtp: drop incorrect amd,imageon 
The SM8150 MTP board does not have magically different GPU than the
SM8150, so it cannot use amd,imageon compatible, also pointed by
dtbs_check:

  sm8150-mtp.dtb: gpu@2c00000: compatible: 'oneOf' conditional failed, one must be fixed:
    ['qcom,adreno-640.1', 'qcom,adreno', 'amd,imageon'] is too long
    'qcom,adreno-640.1' does not match '^qcom,adreno-[0-9a-f]{8}$'
    'qcom,adreno-640.1' does not match '^amd,imageon-200\\.[0-1]$'
    'amd,imageon' was expected

The incorrect amd,imageon compatible was added in commit f30ac26def
("arm64: dts: qcom: add sm8150 GPU nodes") to the SM8150 and later moved
to the SM8150 MTP board in commit 1642ab96ef ("arm64: dts: qcom:
sm8150: Don't start Adreno in headless mode") with an intention to allow
headless mode.  This should be solved via proper driver quirks, not fake
compatibles.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240821140116.436441-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-21 09:47:44 -05:00
Ling Xu
f7b01bfb4b arm64: qcom: sa8775p: Add ADSP and CDSP0 fastrpc nodes 
Add ADSP and CDSP0 fastrpc nodes.

Signed-off-by: Ling Xu <quic_lxu5@quicinc.com>
Reviewed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/20240819045052.2405511-1-quic_lxu5@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-20 17:13:16 -05:00
Konrad Dybcio
5c5edbf461 arm64: dts: qcom: x1e80100: Add USB Multiport controller 
X1E80100 has a multiport controller with 2 HS (eUSB) and 2 SS PHYs
attached to it. It's commonly used for USB-A ports and internally
routed devices. Configure it to support such functionality.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240820-topic-h_mp-v2-2-d88518066372@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-20 17:12:38 -05:00
Bartosz Golaszewski
b45af698d5 arm64: dts: qcom: sa8775p: fix the fastrpc label 
The fastrpc driver uses the label to determine the domain ID and create
the device nodes. It should be "cdsp1" as this is the engine we use here.

Fixes: df54dcb34f ("arm64: dts: qcom: sa8775p: add ADSP, CDSP and GPDSP nodes")
Reported-by: Ekansh Gupta <quic_ekangupt@quicinc.com>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240816102345.16481-2-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-16 10:36:41 -05:00
Varadarajan Narayanan
8312d0f20f arm64: dts: qcom: ipq5332: Add icc provider ability to gcc 
IPQ SoCs dont involve RPM in managing NoC related clocks and
there is no NoC scaling. Linux itself handles these clocks.
However, these should not be exposed as just clocks and align
with other Qualcomm SoCs that handle these clocks from a
interconnect provider.

Hence include icc provider capability to the gcc node so that
peripherals can use the interconnect facility to enable these
clocks. Change USB to use the icc-clk framework for the iface
clock.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20240730054817.1915652-6-quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-15 17:06:55 -05:00
Bjorn Andersson
a7948e0535 Merge branch '20240730054817.1915652-2-quic_varada@quicinc.com' into arm64-for-6.12 
Merge IPQ5332 interconnect binding from the topic branch, to gain access
to the interconnect path defines.
 2024-08-15 17:06:23 -05:00
Varadarajan Narayanan
a500427c84 dt-bindings: interconnect: Add Qualcomm IPQ5332 support 
Add interconnect-cells to clock provider so that it can be
used as icc provider.

Add master/slave ids for Qualcomm IPQ5332 Network-On-Chip
interfaces. This will be used by the gcc-ipq5332 driver
for providing interconnect services using the icc-clk
framework.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20240730054817.1915652-2-quic_varada@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-15 17:05:05 -05:00
Srinivas Kandagatla
be7399872f arm64: dts: qcom: sm8250: move lpass codec macros to use clks directly 
Move lpass codecs va and wsa macros to use the clks directly from
AFE clock controller instead of going via gfm mux like other codec macros
and SoCs.

This makes it more align with the other SoCs and codec macros in this SoC
which take AFE clocks directly. This will also avoid an extra clk mux layer,
provides consistency and avoids the buggy mux driver which will be removed.

This should also fix RB5 audio.

Remove the gfm mux drivers for both audiocc and aoncc.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20240815170542.20754-1-srinivas.kandagatla@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-15 16:59:12 -05:00
AngeloGioacchino Del Regno
1a9544b832 arm64: dts: qcom: msm8998: Add disabled support for LPASS iommu for Q6 
Add support for the LPASS (Q6) SMMU and keep it disabled as this is
used only when the audio DSP is present and used, which is not
mandatory to have.

It is expected for board-specific device-trees to enable this node
if supported.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marc Gonzalez <mgonzalez@freebox.fr>
Link: https://lore.kernel.org/r/20240814-lpass-v1-3-a5bb8f9dfa8b@freebox.fr
[bjorn: s/iface/bus in clock-names, to match binding]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-15 16:20:52 -05:00
Bjorn Andersson
562a2a89ab Merge branch '20240814-lpass-v1-1-a5bb8f9dfa8b@freebox.fr' into arm64-for-6.12 
Merge MSM8998 GCC binding update, to get access to the newly introduced
LPASS clock and GDSC constants.
 2024-08-15 16:11:50 -05:00
AngeloGioacchino Del Regno
015dff12df dt-bindings: clock: gcc-msm8998: Add Q6 and LPASS clocks definitions 
Add definitions for the Q6 BIMC, LPASS core and adsp smmu clocks,
required to enable audio functionality on MSM8998.

Add the GDSC definitions for the LPASS_ADSP_GDSC and LPASS_CORE_GDSC
as a final step to enable the required clock tree for the lpass iommu
and for the audio dsp itself.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marc Gonzalez <mgonzalez@freebox.fr>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240814-lpass-v1-1-a5bb8f9dfa8b@freebox.fr
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-15 16:10:16 -05:00
Barnabás Czémán
a13676eac2 arm64: dts: qcom: msm8976: Add restart node 
Add a pshold restart node what can be found in downstream for
enable to perform restart operations.

Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
Link: https://lore.kernel.org/r/20240807-pshold-v1-1-0fa7927e99ce@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:58:52 -05:00
Bartosz Golaszewski
4f79d0deae arm64: dts: qcom: sa8775p: add CPU idle states 
Add CPU idle-state nodes and power-domains to the .dtsi for SA8775P.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/20240807-sa8775p-idle-states-v1-1-f2b5fcdfa0b0@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:58:21 -05:00
Rob Clark
c46eef2990 arm64: dts: qcom: x1e80100-yoga: Update panel bindings 
Use the correct panel compatible, and wire up enable-gpio.  It is wired
up in the same way as the x1e80100-crd.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Link: https://lore.kernel.org/r/20240806202218.9060-1-robdclark@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:57:40 -05:00
Nikita Travkin
3e813b5408 arm64: dts: qcom: msm8916-samsung-gt58: Enable the touchkeys 
The tablet has two capacitive buttons on the scren bezel. Enable them by
adding the keycodes in the dt.

Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Link: https://lore.kernel.org/r/20240806-msm8916-gt58-tkey-v1-1-8987b06c5921@trvn.ru
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:57:18 -05:00
Bryan O'Donoghue
21927e94ca arm64: dts: qcom: sc8280xp-x13s: Enable RGB sensor 
Enable the main RGB sensor on the Lenovo x13s a five megapixel 2 lane DPHY
MIPI sensor connected to cisphy0.

With the pm8008 patches recently applied to the x13s dtsi we can now also
enable the RGB sensor. Once done we have all upstream support necessary for
the RGB sensor on x13s.

Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20240806-b4-linux-next-24-07-31-camss-sc8280xp-lenovo-rgb-v2-v3-1-199767fb193d@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:57:08 -05:00
Bartosz Golaszewski
2bec6f6a22 arm64: dts: qcom: sa8775p-ride: enable remoteprocs 
Enable all remoteproc nodes on the sa8775p-ride board and point to the
appropriate firmware files.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/20240805-topic-sa8775p-iot-remoteproc-v4-6-86affdc72c04@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:55:24 -05:00
Tengfei Fan
df54dcb34f arm64: dts: qcom: sa8775p: add ADSP, CDSP and GPDSP nodes 
Add nodes for remoteprocs: ADSP, CDSP0, CDSP1, GPDSP0 and GPDSP1 for
SA8775p SoCs.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
[Ling: added the fastrcp nodes]
Co-developed-by: Ling Xu <quic_lxu5@quicinc.com>
Signed-off-by: Ling Xu <quic_lxu5@quicinc.com>
[Bartosz: ported to mainline]
Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/20240805-topic-sa8775p-iot-remoteproc-v4-5-86affdc72c04@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:55:24 -05:00
Tengfei Fan
89817522b1 dt-bindings: mailbox: qcom-ipcc: Add GPDSP0 and GPDSP1 clients 
Add GPDSP0 and GPDSP1 clients for SA8775p platform.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/20240805-topic-sa8775p-iot-remoteproc-v4-2-86affdc72c04@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:55:24 -05:00
Lin, Meng-Bo
469fc2e7a9 arm64: dts: qcom: msm8916-samsung-j3ltetw: Add initial device tree 
The dts and dtsi add support for msm8916 variant of Samsung Galaxy J3
SM-J320YZ smartphone released in 2016.

Add a device tree for SM-J320YZ with initial support for:

- GPIO keys
- SDHCI (internal and external storage)
- USB Device Mode
- UART (on USB connector via the SM5703 MUIC)
- WCNSS (WiFi/BT)
- Regulators
- QDSP6 audio
- Speaker/earpiece/headphones/microphones via digital/analog codec in
  MSM8916/PM8916
- WWAN Internet via BAM-DMUX
- Touchscreen
- Accelerometer

There are different variants of J3, with some differences in MUIC, sensor,
NFC and touch key I2C buses.

The common parts are shared in msm8916-samsung-j3-common.dtsi to reduce
duplication.

Signed-off-by: Lin, Meng-Bo <linmengbo06890@proton.me>
Link: https://lore.kernel.org/r/20240804065854.42437-3-linmengbo06890@proton.me
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:51:50 -05:00
Lin, Meng-Bo
c17427c6ca dt-bindings: qcom: Document samsung,j3ltetw 
Document samsung,j3ltetw bindings used in its device tree.

Signed-off-by: Lin, Meng-Bo <linmengbo06890@proton.me>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240804065854.42437-2-linmengbo06890@proton.me
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:51:50 -05:00
Dmitry Baryshkov
08822cf3de arm64: dts: qcom: sm8350: add refgen regulator 
On SM8350 platform the DSI internally is using the refgen regulator. Add
corresponding device node and link it as a supply to the DSI node.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240804-sm8350-fixes-v1-10-1149dd8399fe@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:50:48 -05:00
Dmitry Baryshkov
5e1cf9f1f3 arm64: dts: qcom: sm8350: add MDSS registers interconnect 
Aside from the MDSS<->MEM interconnect, display devices have separate
interconnect for register access. Add this interconnect to the display
node.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240804-sm8350-fixes-v1-9-1149dd8399fe@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:50:48 -05:00
Danila Tikhonov
0bdadbf5c6 arm64: dts: qcom: sm7125-xiaomi-common: Add reset-gpios for ufs_mem_hc 
The SC7180/SM7125 SoCs have a special pin for UFS reset. Generally, this
pin is the same for all devices on the same SoC because it is hardcoded
in the pinctrl driver. Therefore, it might seem appropriate to add this
pin configuration in sc7180.dtsi. However, this pin is defined in the
device-specific DTS files instead of the SoC-level DTS files in all
Qualcomm DTS. To maintain consistency with this approach, we will follow
the same style.

Add reset-gpios to ufs_mem_hc.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Link: https://lore.kernel.org/r/20240731182412.27966-1-danila@jiaxyga.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:48:17 -05:00
Tengfei Fan
1dd1a6d2b1 arm64: dts: qcom: sa8775p: Add CPU and LLCC BWMON 
Add CPU and LLCC BWMON nodes and their corresponding opp tables for
SA8775p SoC.
SA8775p has two cpu clusters, with each cluster having a set of
CPU-to-LLCC BWMON registers. Consequently, there are two sets of
CPU-to-LLCC registers.

Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
Link: https://lore.kernel.org/r/20240730-add_sa8775p_bwmon-v1-2-f4f878da29ae@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:44:52 -05:00
André Apitzsch
04b2f8d5ae arm64: dts: qcom: msm8939-longcheer-l9100: Add rear flash 
The phone has a Silergy SY7802 flash LED controller.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: André Apitzsch <git@apitzsch.eu>
Link: https://lore.kernel.org/r/20240729-sy7802-v6-1-86bb9083e40b@apitzsch.eu
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:43:11 -05:00
Dmitry Baryshkov
0b7d94e9d1 arm64: dts: qcom: add generic compat string to RPM glink channels 
Add the generic qcom,smd-rpm / qcom,glink-smd-rpm compatible to RPM
nodes to follow the schema.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konradybcio@kernel.org>
Link: https://lore.kernel.org/r/20240729-fix-smd-rpm-v2-5-0776408a94c5@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:41:50 -05:00
Naina Mehta
42a7b7ca4d arm64: dts: qcom: sdx75-idp: enable MPSS remoteproc node 
Enable MPSS remoteproc node on sdx75-idp platform.

Signed-off-by: Naina Mehta <quic_nainmeht@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240709064924.325478-6-quic_nainmeht@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:30:08 -05:00
Naina Mehta
41c72f36b2 arm64: dts: qcom: sdx75: Add remoteproc node 
Add MPSS remoteproc node for SDX75 SoC.

Signed-off-by: Naina Mehta <quic_nainmeht@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240709064924.325478-5-quic_nainmeht@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:30:08 -05:00
Naina Mehta
7a7d98fca6 arm64: dts: qcom: sdx75: update reserved memory regions for mpss 
Rename qdss@88800000 memory region as qlink_logging memory region
and add qdss_mem memory region at address of 0x88500000,
qlink_logging is being added at the memory region at the address
of 0x88800000 as the region is being used by modem firmware.
Since different DSM region size is required for different modem
firmware, split mpss_dsmharq_mem region into 2 separate regions.
This would provide the flexibility to remove the region which is
not required for a particular platform. Based on the modem firmware
either both the regions have to be used or only mpss_dsm_mem has
to be used. Also, reduce the size of mpssadsp_mem region.

Signed-off-by: Naina Mehta <quic_nainmeht@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240709064924.325478-4-quic_nainmeht@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:30:08 -05:00
Krishna Kurapati
b5cbd179f4 arm64: dts: qcom: sa8295p-adp: Enable the four USB Type-A ports 
The multiport USB controller in the SA8295P ADP is connected to four USB
Type-A ports. VBUS for each of these ports are provided by a
TPS2559QWDRCTQ1 regulator, controlled from PMIC GPIOs.

Add the necessary regulators and GPIO configuration to power these.

It seems reasonable that these regulators should be referenced as vbus
supply of usb-a-connector nodes and controlled by e.g. dwc3, but as this
is not supported in Linux today the regulators are left always-on for
now.

Signed-off-by: Krishna Kurapati <quic_kriskura@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240707085624.3411961-1-quic_kriskura@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:22:14 -05:00
Srinivas Kandagatla
6e229f9118 arm64: dts: x1e80100-qcp: fix wsa soundwire port mapping 
Existing way of allocating ports dynamically is linear starting from 1 to
MAX_PORTS. This will not work for x1e80100 as the master ports are
are not mapped in the same order.

Without this fix only one speaker in a pair of speakers will function.

After this fix along with WSA codec changes both the speakers starts
working.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20240626-port-map-v2-6-6cc1c5608cdd@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:19:25 -05:00
Srinivas Kandagatla
d374fafd89 arm64: dts: x1e80100-crd: fix wsa soundwire port mapping 
Existing way of allocating ports dynamically is linear starting from 1 to
MAX_PORTS. This will not work for x1e80100 as the master ports are
are not mapped in the same order.

Without this fix only one speaker in a pair of speakers will function.

After this fix along with WSA codec changes both the speakers starts
working.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-HDK
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Link: https://lore.kernel.org/r/20240626-port-map-v2-5-6cc1c5608cdd@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:19:25 -05:00
Srinivas Kandagatla
8c7dbbed27 arm64: dts: qcom: x1e80100: add soundwire controller resets 
Soundwire controllers (WSA, WSA2, RX, TX) require reset lines to enable
switching clock control from hardware to software.

Add them along with the reset control providers.

Without this reset we might hit fifo under/over run when we try to write to
soundwire device registers.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240624-x1e-swr-reset-v2-3-8bc677fcfa64@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:17:55 -05:00
Vladimir Zapolskiy
9e2ebc5817 arm64: dts: qcom: sm8650: add description of CCI controllers 
Qualcomm SM8650 SoC has three CCI controllers with two I2C busses
connected to each of them.

The CCI controllers on SM8650 are compatible with the ones found on
many other older generations of Qualcomm SoCs.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20240612215835.1149199-5-vladimir.zapolskiy@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:10:14 -05:00
Vladimir Zapolskiy
4f33e6432f arm64: dts: qcom: sm8550: add description of CCI controllers 
Qualcomm SM8550 SoC contains 3 Camera Control Interface controllers
very similar to the ones found on other Qualcomm SoCs.

One noticeable difference is that cci@ac16000 controller provides only
one I2C bus and has an additional control over AON CCI pins gpio208
and gpio209, but this feature is not yet supported in the CCI driver.

Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Link: https://lore.kernel.org/r/20240612215835.1149199-4-vladimir.zapolskiy@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:10:14 -05:00
Ajit Pandey
b87b8df9c0 arm64: dts: qcom: sm4450: add camera, display and gpu clock controller 
Add device node for camera, display and graphics clock controller on
Qualcomm SM4450 platform.

Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240611133752.2192401-9-quic_ajipan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:07:04 -05:00
Bjorn Andersson
b40c6fe821 Merge branch '20240611133752.2192401-1-quic_ajipan@quicinc.com' into arm64-for-6.12 
Merge the SM4450 display, camera and GPU bindings from a topic branch,
to gain access to the clock defines.
 2024-08-14 21:06:25 -05:00
Ajit Pandey
47bad234ee dt-bindings: clock: qcom: add GPUCC clocks on SM4450 
Add device tree bindings for the graphics clock controller on
Qualcomm SM4450 platform.

Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20240611133752.2192401-7-quic_ajipan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:05:15 -05:00
Ajit Pandey
9bf45e4f31 dt-bindings: clock: qcom: add CAMCC clocks on SM4450 
Add device tree bindings for the camera clock controller on
Qualcomm SM4450 platform.

Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240611133752.2192401-5-quic_ajipan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:05:15 -05:00
Ajit Pandey
5115bcaf68 dt-bindings: clock: qcom: add DISPCC clocks on SM4450 
Add device tree bindings for the display clock controller on
Qualcomm SM4450 platform.

Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240611133752.2192401-3-quic_ajipan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-14 21:05:15 -05:00
Bjorn Andersson
3706bcfbdb arm64: dts: qcom: sc8180x: Enable the power key 
No input events are generated from the pressing of the power key on
either Primus or Flex 5G, because the device node isn't enabled.

Give the power key node a label and enable this for the two devices.

Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Tested-by: Steev Klimaszewski <steev@kali.org>
Link: https://lore.kernel.org/r/20240812-sc8180x-pwrkey-enable-v1-1-2bcc22133774@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-08-13 06:12:39 -07:00
Bartosz Golaszewski
4e71c38244 arm64: dts: qcom: sm8650-qrd: use the PMU to power up bluetooth 
Change the HW model in sm8650-qrd.dts to a one closer to reality - where
the WLAN and Bluetooth modules of the WCN7850 are powered by the PMU
inside the package.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Link: https://lore.kernel.org/r/20240709-hci_qca_refactor-v3-6-5f48ca001fed@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-07-31 22:21:42 -05:00
Bjorn Andersson
bb80185cde Merge branch '20240717-dispcc-sm8550-fixes-v2-7-5c4a3128c40b@linaro.org' into arm64-for-6.12 
Merge the SM8550/SM8650 display clock controller binding header file
merge through a topic branch, to ensure the bindings are kept in sync
between clock and DeviceTree source branches.
 2024-07-31 22:07:40 -05:00
Dmitry Baryshkov
99447ef003 dt-bindings: clock: qcom,sm8650-dispcc: replace with symlink 
The display clock controller indices for SM8650 and SM8550 are
completely equal. Replace the header file for qcom,sm8650-dispcc with
the symlink to the qcom,sm8550-dispcc header file.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240717-dispcc-sm8550-fixes-v2-7-5c4a3128c40b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-07-31 22:05:25 -05:00
Raymond Hackley
ccf683fa0c arm64: dts: qcom: msm8916-samsung-fortuna: Add touch keys 
Touch keys feature on fortuna phones are provided by Zinitix touchscreen.
Add property linux,keycodes to enable touch keys.

Signed-off-by: Raymond Hackley <raymondhackley@protonmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240724143230.3804-1-raymondhackley@protonmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-07-31 22:02:10 -05:00
Ankit Sharma
717ca334af arm64: dts: qcom: sa8775p: Add capacity and DPC properties 
The "capacity-dmips-mhz" and "dynamic-power-coefficient" are
used to build Energy Model which in turn is used by EAS to take
placement decisions.

Signed-off-by: Ankit Sharma <quic_anshar@quicinc.com>
Link: https://lore.kernel.org/r/20240731111951.6999-1-quic_anshar@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-07-31 22:01:29 -05:00