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Author SHA1 Message Date
Huang Rui
e68d46484f drm/amd/powerplay: add atomctrl_get_voltage_evv function in ppatomctrl 
The atomctrl_get_voltage_evv function will be used on iceland HW
manager.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-15 12:33:41 -04:00
Huang Rui
0a552a3296 drm/amdgpu: add new definitions into ppsmc.h for iceland 
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-15 12:33:31 -04:00
Huang Rui
be832d848d drm/amd/powerplay: add SMU register macro for future use 
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-15 12:33:21 -04:00
Huang Rui
340efe2898 drm/amdgpu: add ucode_start_address into cgs_firmware_info 
The ucode_start_address would be used on powerplay of iceland.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-15 12:33:10 -04:00
Huang Rui
86a42f04d1 drm/amdgpu: no need load microcode at sdma if powerplay is enabled 
SDMA firmware will be loaded by SMU manager if powerplay is enabled.
So it needn't load at SDMA.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-15 12:33:00 -04:00
Huang Rui
f5a13660cc drm/amdgpu: rename smumgr to smum for dpm 
Rename smumgr.h to smum.h, because smum.h is to align with the dpm of
other chips and we will use "iceland_smumgr" at powerplay in following
patches.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-15 12:32:50 -04:00
Alex Deucher
c02da764da drm/amdgpu: disable GFX PG on CZ/BR/ST 
Still some stability issues under certain workloads.

Reviewed-by: Tom St Denis <tom.stdenis@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-15 12:28:12 -04:00
Matthias Beyer
037d6dfa1e drivers: gpu: drm: amd: powerplay: hwmgr: Remove unused variable 
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Matthias Beyer <mail@beyermatthias.de>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-15 11:45:15 -04:00
Christian König
7129d3ae9d drm/amdgpu: return -ENOSPC when running out of UVD handles 
This is a minor interface change, but clearly won't break anything.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-14 16:46:08 -04:00
Christian König
0c0fdf1439 drm/amdgpu: trace need_flush in grab_vm as well 
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-14 16:46:08 -04:00
Christian König
2ef004d984 drm/amdgpu: always signal all fences 
A little fallout from "drm/amdgpu: sanitize fence numbers", we
sometimes need to signal all fences in the ring.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-14 16:46:07 -04:00
Christian König
090b767e97 drm/amdgpu: check flush fence context instead of same ring v2 
Otherwise we can run into the following situation:

1. Process A grabs ID 1 for ring 0.
2. Process B grabs ID 1 for ring 0.
3. Process A grabs ID 1 for ring 1.
4. Process A tries to reuse ID1 for ring 0 but things he doesn't need to flush.

v2: check the context of the flush fence instead of messing with the owner field.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-14 16:46:07 -04:00
Alex Deucher
d3200be6c4 drm/radeon: support backlight control for UNIPHY3 
Same interface as other UNIPHY blocks

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
 2016-07-14 16:46:06 -04:00
Alex Deucher
dba6c4fa26 drm/amdgpu: support backlight control for UNIPHY3 
Same interface as other UNIPHY blocks

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
 2016-07-14 16:46:06 -04:00
Christian König
6d44565d53 drm/amdgpu: remove usec timeout loop from IB tests 
We already waited for the fence, so waiting for the registers
is completely pointless and just copy & pasted from the ring test.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-14 16:46:05 -04:00
Christian König
22a77cf6d8 drm/amdgpu: cleanup hw reference handling in the IB tests 
Reference should be taken when we make the assignment, not anywhere else.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-14 16:46:05 -04:00
Christian König
0808663517 drm/amdgpu: cleanup UVD coding style 
Cleanup 80 chars limit.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-14 16:46:04 -04:00
Christian König
e5223214b2 drm/amdgpu: allow multiple sessions in the same VCE IB 
We always used updated firmware for amdgpu, so this actually should work fine.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-14 16:46:04 -04:00
Christian König
182830a178 drm/amdgpu: cleanup VCE coding style 
Fix 80 chars issues and remove some dead code as well.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-14 16:46:03 -04:00
Christian König
4f399a0828 drm/amdgpu: sanitize fence numbers 
Looks like the VCE block sometimes still sends nonsense
fence numbers on startup.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-14 16:46:03 -04:00
Alex Deucher
737a44b106 drm/amdgpu/powerplay: endian fixes for ppatomctrl.c 
Atom tables are in LE format.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-08 10:12:10 -04:00
Rex Zhu
b1814a1def drm/amd/powerplay: don't add invalid voltage. 
if atomctrl_get_voltage_evv_on_sclk_ai returns
non zero (fail) in the expansion of the
PP_ASSERT_WITH_CODE macro the continue will
actually do nothing, So invalid voltage will be
added to ppbable.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:24 -04:00
Rex Zhu
ccdbb20a75 drm/amdgpu: add read/write function for GC CAC programming 
Create a GC_CAC_IND_INDEX/DATA pair of funcitons to program
all the CAC registers

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:23 -04:00
Rex Zhu
5e037834eb drm/amd/powerplay: add definitions related to di/dt feature for fiji and polaris. 
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:23 -04:00
Rex Zhu
9a88d22bb0 drm/amd/powerplay: add shared definitions for di/dt feature. 
v1: delete some comflict definitions between polaris and fiji.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:22 -04:00
Ken Wang
a334bc7df0 drm/amdgpu: remove gfx8 registers that vary between asics 
those register mask definitions are different in polaris compare to
former gfx 8 gpus, so remove them from misusing.

Signed-off-by: Ken Wang <Qingqing.Wang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:21 -04:00
Rex Zhu
696b2d7370 drm/amd/powerplay: add mvdd dpm support. 
SMC requires master switch bit to be set.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:21 -04:00
Rex Zhu
d826c982d7 drm/amdgpu: get number of shade engine by cgs interface. 
the num of shade engine was needed to
measure the activity of the graphics core
and to enable di/dt feature.

Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:20 -04:00
Alex Deucher
33b7ed0122 drm/amdgpu: remove more of the ring backup code 
Not used anymore.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:19 -04:00
Tom St Denis
bb06d7ef99 drm/amd/powerplay: Unify family defines 
s/AMD_FAMILY_/AMDGPU_FAMILY_/

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:19 -04:00
Chunming Zhou
40019dc4a3 drm/amdgpu: clean up ring_backup code, no need more 
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:18 -04:00
Chunming Zhou
1f46508721 drm/amdgpu: ib test first after gpu reset 
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:18 -04:00
Chunming Zhou
aa1c890008 drm/amdgpu: recovery hw jobs when gpu reset V3 
V3: directly use pd_addr.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:17 -04:00
Chunming Zhou
192b7dcbb5 drm/amdgpu: abstract amdgpu_vm_is_gpu_reset 
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:16 -04:00
Chunming Zhou
fd53be302f drm/amdgpu: add a bool to specify if needing vm flush V2 
which avoids job->vm_pd_addr be changed.

V2: pass job structure to amdgpu_vm_grab_id and amdgpu_vm_flush directly.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:16 -04:00
Chunming Zhou
ec75f573c3 drm/amdgpu: add amd_sched_job_recovery 
Which is to recover hw jobs when gpu reset.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:15 -04:00
Chunming Zhou
2200edac74 drm/amdgpu: force completion for gpu reset 
After all hw jobs are reset, hw fence is meaningless, so force_completion

Cc: William Lewis <minutemaidpark@hotmail.com>
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:15 -04:00
Chunming Zhou
a3c47d6bdc drm/amdgpu: block ttm first before parking scheduler 
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:14 -04:00
Chunming Zhou
e686e75dac drm/amd: add amd_sched_hw_job_reset 
amd_sched_hw_job_reset will remove callback from hw fence.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:13 -04:00
Chunming Zhou
754ce0fa55 drm/amd: add parent for sched fence 
Parent of sched fence is hw fence which is to signal sched fence.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:13 -04:00
Chunming Zhou
f263ec622f drm/amdgpu: remove evict vram 
Previous vm fault is since page talbe losts connection with vmid after gpu reset.
Now the issue is fixed by recovery. No need more.

If we want to save vram for some EDC card, we will need to consider a complete solution.

Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:12 -04:00
Chunming Zhou
c7c5fbcdc3 drm/amdgpu: put old hw fence of job if gpu reset 
Signed-off-by: Chunming Zhou <David1.Zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:12 -04:00
Christian König
595a9cd68c drm/amdgpu: remove fence parameter from amd_sched_job_init 
We return the fence as part of the job structur anyway,
no need to do this twice.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:11 -04:00
Christian König
a5fb4ec29c drm/amdgpu: earlier free SA resources 
Keep the time we don't have a fence associated with the resource smaller.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:10 -04:00
Christian König
a79a5bdcef drm/amdgpu: shorten amdgpu_job_free_resources 
The fence and the sync object are not hardware resources.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:10 -04:00
Christian König
b5f5acbc87 drm/amdgpu: fix user fence handling once more 
Same problem as with the VM page tables. The user fence address must be
determined before the job is scheduled, not when the IB is executed.

This fixes a security problem where user fences could be used to overwrite
any part of VRAM.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:09 -04:00
Tom St Denis
5662815950 drm/amd/amdgpu: Add bank selection for MMIO debugfs (v3) 
(v2) Added INSTANCE selector
(v3) Changed order of bank selectors

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:09 -04:00
Tom St Denis
1e0514131d drm/amd/amdgpu: Add gca config debug entry (v4) 
A binary entry that lists GCA configuration data (and can be
read by umr).

(v2) Use kmalloc instead of vmalloc
(v3) Minor indentation correction
(v4) agd: Squash in kmalloc fix

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:08 -04:00
Tom St Denis
9559ef5b12 drm/amd/gfx: add instance field to select_se_sh (v3) 
Add ability to specify instance in select_se_sh callback.
Defaults to 0xffffffff all over the driver.

(v2) Don't enable INSTANCE_BROADCAST by default
(v3) Style changes

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:07 -04:00
Lyude
b636a1b3d6 drm/amdgpu: Poll for both connect/disconnect on analog connectors 
DRM_CONNECTOR_POLL_CONNECT only enables polling for connections, not
disconnections. Because of this, we end up losing hotplug polling for
analog connectors once they get connected.

Easy way to reproduce:
 - Grab a machine with an AMD GPU and a VGA port
 - Plug a monitor into the VGA port, wait for it to update the connector
   from disconnected to connected
 - Disconnect the monitor on VGA, a hotplug event is never sent for the
   removal of the connector.

Originally, only using DRM_CONNECTOR_POLL_CONNECT might have been a good
idea since doing VGA polling can sometimes result in having to mess with
the DAC voltages to figure out whether or not there's actually something
there since VGA doesn't have HPD. Doing this would have the potential of
showing visible artifacts on the screen every time we ran a poll while a
VGA display was connected. Luckily, amdgpu_vga_detect() only resorts to
this sort of polling if the poll is forced, and DRM's polling helper
doesn't force it's polls.

Additionally, this removes some assignments to connector->polled that
weren't actually doing anything.

Cc: stable@vger.kernel.org
Signed-off-by: Lyude <cpaul@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2016-07-07 15:06:07 -04:00