Double Buffered LUT registers can be programmed in the active region.
This patch implements the MMIO path for it. Program the registers after
evading vblank. The HW latches on to the registers after delayed vblank.
It takes around 1024 cdclk cycles(~one scanline) for this.
Following assumptions have been made while making this change
- Current vblank evasion time is sufficient for programming
the LUT registers.
- Current guardband calculation would be sufficient for the HW
to latch on to the new values
v2: move loading LUTs to commit_pipe_post_planes() since a vblank
evasion failure for this is probably less drastic than
for plane programming. (Ville)
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://lore.kernel.org/r/20250523062041.166468-10-chaitanya.kumar.borah@intel.com
With addition of double buffered GAMMA registers in PTL, we can now
program them in the active region. Use GOSUB instruction of DSB to
program them.
It is done in the following steps:
1. intel_color_prepare_commit()
- If the platform supports, prepare a dsb instance (dsb_color)
hooked to DSB0.
- Add all the register write instructions to dsb_color through
the load_lut() hook
- Do not add the vrr_send_push() logic to the buffer as it
should be taken care by dsb_commit instance of DSB0
- Finish preparation of the buffer by aligning it to 64 bit
2. intel_atomic_dsb_finish()
- Add the gosub instruction into the dsb_commit instance of DSB0
using intel_dsb_gosub()
- If needed, add the vrr_send_push() logic to dsb_commit after it
v2: Refactor code to simplify commit completion flow.
Add some helpers along the way (Ville)
v3: s/doubled/double and add display to commit message prefix (Uma)
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://lore.kernel.org/r/20250523062041.166468-9-chaitanya.kumar.borah@intel.com
Add support for the new GOSUB DSB instruction (available on ptl+),
which instructs the DSB to jump to a different buffer, execute
the commands there, and then return execution to the next
instruction in the original buffer.
There are a few alignment related workarounds that need to
be dealt with when emitting GOSUB instruction.
v2: Right shift head and tail pointer passed to gosub command (chaitanya)
v3: Add macro for right shifting head/tail pointers (Animesh)
v4: Fix typo in commit message (Uma)
Add comments explaining why right shifting htp is needed (Animesh)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Link: https://lore.kernel.org/r/20250523062041.166468-5-chaitanya.kumar.borah@intel.com
Adjust the enabling/disabling steps of the DP audio SDP splitting
according to a recent Bspec update. This moves the enabling to the audio
codec enable sequence after the transcoder is enabled and disables SDP
splitting explicitly during the audio disable sequence.
Bspec requires waiting for a vblank event after the transcoder is
enabled and before SDP splitting is enabled. There is no need for an
explicit wait for this, since after the transcoder is enabled this
vblank event is guaranteed to have happened via a flip done wait (see
intel_atomic_commit_tail() -> drm_atomic_helper_wait_for_flip_done()).
The bspec update is for LNL+ only, but the HW team clarified that this
has been always the intended sequence on all platforms and bspec will be
updated everywhere accordingly.
The way SDP splitting was originally enabled matched the version of
bspec at that time. Adding here the Fixes: line still, since this
change fixes a FIFO underrun on PTL during output enabling when DSC is
enabled.
Bspec: 49283, 68943
Fixes: 8853750dba ("drm/i915: Enable SDP split for DP2.0")
Cc: Vinod Govindapillai <vinod.govindapillai@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://lore.kernel.org/r/20250520142219.1688401-1-imre.deak@intel.com
The future goal is to have intel_display_device_probe() create struct
intel_display. As the first step, postpone xe->display initialization
right before that call. This is the same location as in i915.
There's a subtle functional change here: xe->display will now be
initialized only if xe->info.probe_display.
The xe_display_create() function becomes empty, and can be removed. Move
its documentation to xe_display_probe()
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Link: https://lore.kernel.org/r/6c3075739d84cecea258d686c3ef38455a61191c.1747397638.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Rename crtc_get_shared_dpll to take into the individual PLL framework
which came in at DISPLAY_VER >= 14.
Also having shared dpll stuff also in intel_dpll.c is just confusing.
--v2
-Change naming to dpll_global to keep consistency with rest of the
naming
--v3
-Just use intel_dpll [Jani]
--v4
-Modify commit message [Jani]
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://lore.kernel.org/r/20250515071801.2221120-9-suraj.kandpal@intel.com
Rename intel_shared_dpll to intel_dpll to represent both
shared and individual dplls. Since from MTL each PHY has it's
own PLL making the shared PLL naming a little outdated. In an
effort to make this framework accepting of future changes this
needs to be done.
--v2
-Use intel_dpll_global to make sure names start with the filename
[Jani/Ville]
-Explain the need of this rename [Jani]
--v3
-Just keep it intel_dpll [Jani]
--v4
-Fix comment [Jani]
-Use just num_dpll and dplls [Jani]
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://lore.kernel.org/r/20250515071801.2221120-7-suraj.kandpal@intel.com
Rename intel_shared_dpll_funcs to intel_dpll_funcs
since it needs to represent both shared and individual
dplls.
--v2
-Change intel_global_dpll to intel_dpll_global to be more
in line with the naming standard where the name should
start with the file name [Jani]
--v3
-Drop shared and global altogether [Jani]
--v4
-Keep declarations sorted [Jani]
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Link: https://lore.kernel.org/r/20250515071801.2221120-6-suraj.kandpal@intel.com
The register EMP_AS_SDP_TL (MTL) was introduced for configuring the
double buffering point and transmission line for all
HDMI2.1 Extended Metadata Packets (VT-EMP for VRR, CVT-EMP for DSC etc).
This was also intended to be configured for DP to HDMI2.1 PCON to
support VRR.
From BMG and LNL+ onwards, this register was extended to Display Port
Adaptive Sync SDP to have a common register to configure double
buffering point and transmission line for both HDMI EMPs and DP VRR related
packets.
Currently, we do not support VRR for either native HDMI or via PCON.
However we need to configure this for DP SDP case. As per the spec,
program the register to set Vsync start as the double buffering point
for DP AS SDP.
v2:
-Make the helper more readable. (Jani)
-Add more information in commit message and comment.
Bspec:70984, 71197
Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Tested-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
Link: https://lore.kernel.org/r/20250505033911.393628-1-ankit.k.nautiyal@intel.com
