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93847 Commits

Author SHA1 Message Date
Fabio Estevam
db07ce5da8 drm/msm/a2xx: Call adreno_gpu_init() earlier 
The adreno_is_a20x() and adreno_is_a225() functions rely on the
GPU revision, but such information is retrieved inside adreno_gpu_init(),
which is called afterwards.

Fix this problem by caling adreno_gpu_init() earlier, so that
the GPU information revision is available when adreno_is_a20x()
and adreno_is_a225() run.

Tested on a imx53-qsb board.

Fixes: 21af872cd8 ("drm/msm/adreno: add a2xx")
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/543456/
Signed-off-by: Rob Clark <robdclark@chromium.org>
 2023-08-07 14:39:24 -07:00
Konrad Dybcio
1bfa795145 drm/msm/a6xx: Fix up GMU region reservations 
Change the order of region allocations to make the addresses match
downstream. This shouldn't matter very much, but helps eliminate one
more difference when comparing register accesses.

Also, make the log region 16K long. That's what it is, unconditionally
on A6xx and A7xx.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/543338/
Signed-off-by: Rob Clark <robdclark@chromium.org>
 2023-08-07 14:32:10 -07:00
Konrad Dybcio
6ab410e0ff drm/msm/a6xx: Improve GMU force shutdown sequence 
The GMU force shutdown sequence involves some additional register cleanup
which was not implemented previously. Do so.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/543340/
Signed-off-by: Rob Clark <robdclark@chromium.org>
 2023-08-07 14:32:10 -07:00
Konrad Dybcio
5e46ad83db drm/msm/a6xx: Ensure clean GMU state in a6xx_gmu_fw_start 
While it's not very well understood, there is some sort of a fault
handler implemented in the GMU firmware which triggers when a certain
bit is set, resulting in the M3 core not booting up the way we expect
it to.

Write a magic value to a magic register to hopefully prevent that
from happening.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/543335/
Signed-off-by: Rob Clark <robdclark@chromium.org>
 2023-08-07 14:32:10 -07:00
Konrad Dybcio
29af760545 drm/msm/a6xx: Skip empty protection ranges entries 
Some specific SKUs leave certain protection range registers empty.
Allow for that behavior.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/543334/
Signed-off-by: Rob Clark <robdclark@chromium.org>
 2023-08-07 14:30:49 -07:00
Konrad Dybcio
02a726fc6b drm/msm/a6xx: Use descriptive bitfield names for CP_PROTECT_CNTL 
We have the necessary information, so explain which bit does what.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/543332/
Signed-off-by: Rob Clark <robdclark@chromium.org>
 2023-08-07 14:30:49 -07:00
Konrad Dybcio
b3ba797e45 drm/msm/a6xx: Add some missing header definitions 
Add a definition of the GMU_AHB_FENCE_STATUS_CLR reg and CP_PROTECT_CNTL
bitfields.

This may be substituted with a mesa header sync.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/543330/
Signed-off-by: Rob Clark <robdclark@chromium.org>
 2023-08-07 14:30:49 -07:00
Rob Clark
3bf8466567 drm/msm/a6xx: Fix misleading comment 
The range is actually len+1.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/545099/
 2023-08-07 14:28:06 -07:00
Rob Clark
90b593ce1c drm/msm/adreno: Switch to chip-id for identifying GPU 
Since the revision becomes an opaque identifier with future GPUs, move
away from treating different ranges of bits as having a given meaning.
This means that we need to explicitly list different patch revisions in
the device table.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549782/
 2023-08-07 14:22:36 -07:00
Rob Clark
47bd37f948 drm/msm/adreno: Move adreno info to config 
Let's just stash it in adreno_platform_config rather than looking it up
in N different places.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549777/
 2023-08-07 14:21:19 -07:00
Rob Clark
8825f59692 drm/msm/adreno: Add helper for formating chip-id 
This is used in a few places, including one that is parsed by userspace
tools.  So let's standardize it a bit better.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549774/
 2023-08-07 14:21:19 -07:00
Rob Clark
67133dc086 drm/msm/adreno: Add adreno family 
Sometimes it is useful to know the sub-generation (or "family").  And in
any case, this helps us get away from infering the generation from the
numerical chip-id.

v2: Fix is_a2xx() typo

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549773/
 2023-08-07 14:21:19 -07:00
Rob Clark
75a5227c0d drm/msm/adreno: Bring the a630 family together 
All of these are derivatives of a630.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549770/
 2023-08-07 14:21:18 -07:00
Rob Clark
c928a05e44 drm/msm/adreno: Move speedbin mapping to device table 
This simplifies the code.

v2: Use a table of structs instead of flat uint32_t[]

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549769/
 2023-08-07 14:19:16 -07:00
Rob Clark
f30a648d87 drm/msm/adreno: Allow SoC specific gpu device table entries 
There are cases where there are differences due to SoC integration.
Such as cache-coherency support, and (in the next patch) e-fuse to
speedbin mappings.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549767/
 2023-08-07 14:19:16 -07:00
Rob Clark
155668ef41 drm/msm/adreno: Use quirk to identify cached-coherent support 
It is better to explicitly list it.  With the move to opaque chip-id's
for future devices, we should avoid trying to infer things like
generation from the numerical value.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549765/
 2023-08-07 14:19:16 -07:00
Rob Clark
459f9e26e7 drm/msm/adreno: Use quirk identify hw_apriv 
Rather than just open coding a list of gpu-id matches.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549764/
 2023-08-07 14:19:16 -07:00
Rob Clark
f4f1c70781 drm/msm/adreno: Remove redundant revn param 
This just duplicates what is in adreno_info, and can cause confusion if
used before it is set.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549761/
 2023-08-07 14:19:15 -07:00
Rob Clark
6391030df0 drm/msm/adreno: Remove redundant gmem size param 
Even in the ocmem case, the allocated ocmem buffer size should match the
requested size.

v2: Move stray hunk to previous patch, make OCMEM size mismatch an error
    condition.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549759/
 2023-08-07 14:19:15 -07:00
Rob Clark
832ee64deb drm/msm/adreno: Remove GPU name 
No real need to have marketing names in the kernel.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549757/
 2023-08-07 14:19:15 -07:00
Rob Clark
fa0f4d0735 Merge branch 'msm-fixes' into msm-next 
Back-merge msm-fixes to resolve conflicts.

Signed-off-by: Rob Clark <robdclark@chromium.org>
 2023-08-07 14:10:18 -07:00
Dmitry Baryshkov
d93cf453f5 drm/msm/dpu: fix the irq index in dpu_encoder_phys_wb_wait_for_commit_done 
Since commit 1e7ac595fa ("drm/msm/dpu: pass irq to
dpu_encoder_helper_wait_for_irq()") the
dpu_encoder_phys_wb_wait_for_commit_done expects the IRQ index rather
than the IRQ index in phys_enc->intr table, however writeback got the
older invocation in place. This was unnoticed for several releases, but
now it's time to fix it.

Fixes: d7d0e73f7d ("drm/msm/dpu: introduce the dpu_encoder_phys_* for writeback")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/550924/
Link: https://lore.kernel.org/r/20230802100426.4184892-2-dmitry.baryshkov@linaro.org
 2023-08-04 18:15:17 +03:00
Dmitry Baryshkov
34202be952 drm/msm/dpu: initialise clk_rate to 0 in _dpu_core_perf_get_core_clk_rate 
When removing the core perf tune overrides, I also occasionaly removed the
initialisation of the clk_rate variable. Initialise it to 0 to let max()
correctly calculate the maximum of requested clock rates.

Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
Fixes: 6a4bc73915 ("drm/msm/dpu: drop separate dpu_core_perf_tune overrides")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/551321/
Link: https://lore.kernel.org/r/20230804094804.36053-1-dmitry.baryshkov@linaro.org
 2023-08-04 18:10:55 +03:00
Jiapeng Chong
b0fe701050 drm/msm/dpu: clean up some inconsistent indenting 
No functional modification involved.

drivers/gpu/drm/msm/disp/dpu1/dpu_core_perf.c:183 dpu_core_perf_crtc_check() warn: inconsistent indenting.

Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6096
Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/551313/
Link: https://lore.kernel.org/r/20230804075746.77435-1-jiapeng.chong@linux.alibaba.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
 2023-08-04 16:17:09 +03:00
Daniel Vetter
fd0ad3b236 drm/msm/mdp5: Don't leak some plane state 
Apparently no one noticed that mdp5 plane states leak like a sieve
ever since we introduced plane_state->commit refcount a few years ago
in 21a01abbe3 ("drm/atomic: Fix freeing connector/plane state too
early by tracking commits, v3.")

Fix it by using the right helpers.

Fixes: 21a01abbe3 ("drm/atomic: Fix freeing connector/plane state too early by tracking commits, v3.")
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Rob Clark <robdclark@gmail.com>
Cc: Abhinav Kumar <quic_abhinavk@quicinc.com>
Cc: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: freedreno@lists.freedesktop.org
Reported-and-tested-by: dorum@noisolation.com
Cc: dorum@noisolation.com
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/551236/
Link: https://lore.kernel.org/r/20230803204521.928582-1-daniel.vetter@ffwll.ch
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
 2023-08-04 16:15:49 +03:00
Jessica Zhang
fdcb8fe0c9 drm/msm/dpu: Drop encoder vsync_event 
Drop vsync_event and vsync_event_work handlers as they are unnecessary.
In addition drop the dpu_enc_ktime_template event class as it will be
unused after the vsync_event handlers are dropped.

Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/550983/
Link: https://lore.kernel.org/r/20230802-encoder-cleanup-v2-1-5bfdec0ce765@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
 2023-08-04 16:15:08 +03:00
Dmitry Baryshkov
57a1ca6cf7 drm/msm/dpu: fix DSC 1.2 enc subblock length 
Both struct dpu_dsc_sub_blks instances declare enc subblock length to be
0x100, while the actual length is 0x9c (last register having offset 0x98).
Reduce subblock length to remove the empty register space from being
dumped.

Fixes: 0d1b10c633 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets")
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/550999/
Link: https://lore.kernel.org/r/20230802183655.4188640-2-dmitry.baryshkov@linaro.org
 2023-08-03 14:17:32 +03:00
Dmitry Baryshkov
e550ad0e5c drm/msm/dpu: fix DSC 1.2 block lengths 
All DSC_BLK_1_2 declarations incorrectly pass 0x29c as the block length.
This includes the common block itself, enc subblocks and some empty
space around. Change that to pass 0x4 instead, the length of common
register block itself.

Fixes: 0d1b10c633 ("drm/msm/dpu: add DSC 1.2 hw blocks for relevant chipsets")
Reported-by: Ryan McCann <quic_rmccann@quicinc.com>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Patchwork: https://patchwork.freedesktop.org/patch/550998/
Link: https://lore.kernel.org/r/20230802183655.4188640-1-dmitry.baryshkov@linaro.org
 2023-08-03 14:17:32 +03:00
Jonathan Marek
42d0d253ed drm/msm/dpu: increase memtype count to 16 for sm8550 
sm8550 has 16 vbif clients.

This fixes the extra 2 clients (DMA4/DMA5) not having their memtype
initialized. This fixes DMA4/DMA5 planes not displaying correctly.

Fixes: efcd010772 ("drm/msm/dpu: add support for SM8550")
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8550-QRD
Patchwork: https://patchwork.freedesktop.org/patch/550968/
Link: https://lore.kernel.org/r/20230802134900.30435-1-jonathan@marek.ca
[DB: fixed the Fixes tag]
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
 2023-08-03 14:03:57 +03:00
Dmitry Baryshkov
3d5199a173 drm/msm/dpu: drop dpu_core_perf_destroy() 
This function does nothing, just clears one struct field. Drop it now.

Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/550210/
Link: https://lore.kernel.org/r/20230730010102.350713-11-dmitry.baryshkov@linaro.org
 2023-08-02 12:39:27 +03:00
Dmitry Baryshkov
4161ec7e93 drm/msm/dpu: move max clock decision to dpu_kms. 
dpu_core_perf should not make decisions on the maximum possible core
clock rate. Pass the value from dpu_kms_hw_init() and drop handling of
core_clk from dpu_core_perf.c

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/550201/
Link: https://lore.kernel.org/r/20230730010102.350713-10-dmitry.baryshkov@linaro.org
 2023-08-02 12:39:27 +03:00
Dmitry Baryshkov
d64d83806a drm/msm/dpu: remove extra clk_round_rate() call 
The dev_pm_opp_set_rate() already contains a call for clk_round_rate for
the passed value. Stop calling it manually from
_dpu_core_perf_get_core_clk_rate(). It is slightly incorrect to call it
this way, as we should round the final calculated clock rate rather than
rounding all the intermediate values.

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/550212/
Link: https://lore.kernel.org/r/20230730010102.350713-9-dmitry.baryshkov@linaro.org
 2023-08-02 12:39:26 +03:00
Dmitry Baryshkov
7a73594029 drm/msm/dpu: remove unused fields from struct dpu_core_perf 
Remove dpu_core_perf::dev and dpu_core_perf::debugfs_root fields, they
are not used by the code.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/550200/
Link: https://lore.kernel.org/r/20230730010102.350713-8-dmitry.baryshkov@linaro.org
 2023-08-02 12:39:26 +03:00
Dmitry Baryshkov
779f336ed4 drm/msm/dpu: use dpu_perf_cfg in DPU core_perf code 
Simplify dpu_core_perf code by using only dpu_perf_cfg instead of using
full-featured catalog data.

Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/550198/
Link: https://lore.kernel.org/r/20230730010102.350713-7-dmitry.baryshkov@linaro.org
 2023-08-02 12:39:26 +03:00
Dmitry Baryshkov
716f0d4cac drm/msm/dpu: drop the dpu_core_perf_crtc_update()'s stop_req param 
The stop_req is true only in the dpu_crtc_disable() case, when
crtc->enable has already been set to false. This renders the stop_req
argument useless. Remove it completely.

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/550206/
Link: https://lore.kernel.org/r/20230730010102.350713-6-dmitry.baryshkov@linaro.org
 2023-08-02 12:39:26 +03:00
Dmitry Baryshkov
a6239e65c8 drm/msm/dpu: rework indentation in dpu_core_perf 
dpu_core_perf.c contains several multi-line conditions which are hard to
comprehent because of the indentation. Rework the identation of these
conditions to make it easier to understand them.

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/550197/
Link: https://lore.kernel.org/r/20230730010102.350713-5-dmitry.baryshkov@linaro.org
 2023-08-02 12:39:26 +03:00
Dmitry Baryshkov
6a4bc73915 drm/msm/dpu: drop separate dpu_core_perf_tune overrides 
The values in struct dpu_core_perf_tune are fixed per the core perf
mode. Drop the 'tune' values and substitute them with known values when
performing perf management.

Note: min_bus_vote was not used at all, so it is just silently dropped.

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/550208/
Link: https://lore.kernel.org/r/20230730010102.350713-4-dmitry.baryshkov@linaro.org
 2023-08-02 12:39:26 +03:00
Dmitry Baryshkov
808c92df65 drm/msm/dpu: bail from _dpu_core_perf_crtc_update_bus if there are no ICC paths 
Skip bandwidth aggregation and return early if there are no interconnect
paths defined for the DPU device.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/550195/
Link: https://lore.kernel.org/r/20230730010102.350713-3-dmitry.baryshkov@linaro.org
 2023-08-02 12:39:26 +03:00
Dmitry Baryshkov
f15de4f624 drm/msm/dpu: drop enum dpu_core_perf_data_bus_id 
Drop the leftover of bus-client -> interconnect conversion, the enum
dpu_core_perf_data_bus_id.

Fixes: cb88482e25 ("drm/msm/dpu: clean up references of DPU custom bus scaling")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/550194/
Link: https://lore.kernel.org/r/20230730010102.350713-2-dmitry.baryshkov@linaro.org
 2023-08-02 12:39:26 +03:00
Dmitry Baryshkov
7b4a727e84 drm/msm/dpu: drop BWC features from DPU_MDP_foo namespace 
The feature bits DPU_MDP_BWC, DPU_MDP_UBWC_1_0, and DPU_MDP_UBWC_1_5 are
not used by the driver, drop them completely.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/550056/
Link: https://lore.kernel.org/r/20230728213320.97309-8-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
 2023-08-02 12:37:53 +03:00
Dmitry Baryshkov
1613c5fddd drm/msm/dpu: drop UBWC configuration 
As the DPU driver has switched to fetching data from MDSS driver, we can
now drop the UBWC and highest_bank_bit parts of the DPU hw catalog.

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/550058/
Link: https://lore.kernel.org/r/20230728213320.97309-7-dmitry.baryshkov@linaro.org
 2023-08-02 12:37:36 +03:00
Dmitry Baryshkov
a2e87e9ef8 drm/msm/dpu: use MDSS data for programming SSPP 
Switch to using data from MDSS driver to program the SSPP fetch and UBWC
configuration. As a side-effect, this also swithes the DPU driver from
DPU_HW_UBWC_VER_xx values to the UBWC_x_y enum, which reflects
the hardware register values.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/550054/
Link: https://lore.kernel.org/r/20230728213320.97309-6-dmitry.baryshkov@linaro.org
 2023-08-02 12:37:36 +03:00
Dmitry Baryshkov
6f410b2462 drm/msm/mdss: populate missing data 
As we are going to use MDSS data for DPU programming, populate missing
MDSS data. The UBWC 1.0 and no UBWC cases do not require MDSS
programming, so skip them.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/550055/
Link: https://lore.kernel.org/r/20230728213320.97309-5-dmitry.baryshkov@linaro.org
 2023-08-02 12:37:36 +03:00
Dmitry Baryshkov
71e00fc0af drm/msm/mdss: export UBWC data 
DPU programming requires knowledge of some of UBWC parameters. This
results in duplication of UBWC data between MDSS and DPU drivers. Export
the required data from MDSS driver.

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/550052/
Link: https://lore.kernel.org/r/20230728213320.97309-4-dmitry.baryshkov@linaro.org
 2023-08-02 12:37:36 +03:00
Dmitry Baryshkov
cab5b40633 drm/msm/mdss: rename ubwc_version to ubwc_enc_version 
Rename the ubwc_version field to ubwc_enc_version, it denotes the
version of the UBWC encoder, not the "UBWC version".

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/550051/
Link: https://lore.kernel.org/r/20230728213320.97309-3-dmitry.baryshkov@linaro.org
 2023-08-02 12:37:36 +03:00
Dmitry Baryshkov
0fbe7c7d36 drm/msm/mdss: correct UBWC programming for SM8550 
The SM8550 platform employs newer UBWC decoder, which requires slightly
different programming.

Fixes: a2f33995c1 ("drm/msm: mdss: add support for SM8550")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/550049/
Link: https://lore.kernel.org/r/20230728213320.97309-2-dmitry.baryshkov@linaro.org
 2023-08-02 12:37:36 +03:00
Dmitry Baryshkov
edb34ac1f6 drm/msm/dpu: drop compatibility INTR defines 
While reworking interrupts masks, it was easier to keep old
MDP_INTFn_7xxx_INTR and MDP_INTFn_7xxx_TEAR_INTR symbols. Now it is time
to drop them and use unified symbol names.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549656/
Link: https://lore.kernel.org/r/20230727144543.1483630-6-dmitry.baryshkov@linaro.org
 2023-08-02 12:36:33 +03:00
Dmitry Baryshkov
40f9cedf54 drm/msm/dpu: drop now-unused mdss_irqs field from hw catalog 
Now as the list of the interrupts is constructed from the catalog
data, drop the mdss_irqs field from catalog.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549659/
Link: https://lore.kernel.org/r/20230727144543.1483630-5-dmitry.baryshkov@linaro.org
 2023-08-02 12:36:33 +03:00
Dmitry Baryshkov
bf8198cc3b drm/msm/dpu: autodetect supported interrupts 
Declaring the mask of supported interrupts proved to be error-prone. It
is very easy to add a bit with no corresponding backing block or to miss
the INTF TE bit. Replace this with looping over the enabled INTF blocks
to setup the irq mask.

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549654/
Link: https://lore.kernel.org/r/20230727144543.1483630-4-dmitry.baryshkov@linaro.org
 2023-08-02 12:36:33 +03:00
Dmitry Baryshkov
370891f0d9 drm/msm/dpu: split interrupt address arrays 
There is no point in having a single enum (and a single array) for both
DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
enum and two IRQ address arrays.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Fixes: c731461322 ("drm/msm: Add missing struct identifier")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/549653/
Link: https://lore.kernel.org/r/20230727144543.1483630-3-dmitry.baryshkov@linaro.org
 2023-08-02 12:36:32 +03:00