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Author SHA1 Message Date
Dave Jiang
cf4ac3fef3 dmaengine: idxd: fix lockdep warning on device driver removal 
Jacob reported that with lockdep debug turned on, idxd_device_driver
removal causes kernel splat from lock assert warning for
idxd_device_wqs_clear_state(). Make sure
idxd_device_wqs_clear_state() holds the wq lock for each wq when
cleaning the wq state. Move the call outside of the device spinlock.

Reported-by: Jacob Pan <jacob.jun.pan@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/165231364426.986304.9294302800482492780.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-05-16 18:19:29 +05:30
Dave Jiang
42a1b73852 dmaengine: idxd: Separate user and kernel pasid enabling 
The idxd driver always gated the pasid enabling under a single knob and
this assumption is incorrect. The pasid used for kernel operation can be
independently toggled and has no dependency on the user pasid (and vice
versa). Split the two so they are independent "enabled" flags.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/165231431746.986466.5666862038354800551.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-05-16 18:19:29 +05:30
Geert Uytterhoeven
b965182aee dt-bindings: renesas,rcar-dmac: R-Car V3U is R-Car Gen4 
Despite the name, R-Car V3U is the first member of the R-Car Gen4
family.  Hence move its compatible value to the R-Car Gen4 section.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/e6e4cf701f3a43b061b9c3f7f0adc4d6addd4722.1651497024.git.geert+renesas@glider.be
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-05-16 17:00:55 +05:30
Christophe JAILLET
aab08c1aac dmaengine: idxd: Fix the error handling path in idxd_cdev_register() 
If a call to alloc_chrdev_region() fails, the already allocated resources
are leaking.

Add the needed error handling path to fix the leak.

Fixes: 42d279f913 ("dmaengine: idxd: add char driver to expose submission portal to userland")
Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Acked-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/1b5033dcc87b5f2a953c413f0306e883e6114542.1650521591.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-05-16 16:58:32 +05:30
Akhil R
461cd3709f dmaengine: tegra: Use platform_get_irq() to get IRQ resource 
Use platform_irq_get() instead platform_get_resource() for IRQ resource
to fix the probe failure. platform_get_resource() fails to fetch the IRQ
resource as it might not be ready at that time.

platform_irq_get() is also the recommended way to get interrupt as it
directly gives the IRQ number and no conversion from resource is
required.

Fixes: ee17028009 ("dmaengine: tegra: Add tegra gpcdma driver")
Reported-by: Jonathan Hunter <jonathanh@nvidia.com>
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Link: https://lore.kernel.org/r/20220505091440.12981-1-akhilrajeev@nvidia.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-05-16 16:58:10 +05:30
Yunbo Yu
99faef48e7 dmaengine: mv_xor_v2 : Move spin_lock_bh() to spin_lock() 
It is unnecessary to call spin_lock_bh() for that you are already
in a tasklet.

Signed-off-by: Yunbo Yu <yuyunbo519@gmail.com>
Link: https://lore.kernel.org/r/20220420122754.148359-1-yuyunbo519@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-22 12:56:41 +05:30
Dave Jiang
63c14ae6c1 dmaengine: idxd: refactor wq driver enable/disable operations 
Move the core driver operations from wq driver to the drv_enable_wq() and
drv_disable_wq() functions. The move should reduce the wq driver's
knowledge of the core driver operations and prevent code confusion for
future wq drivers.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/165047301643.3841827.11222723219862233060.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-22 12:54:20 +05:30
Jayesh Choudhary
b21fe492a3 dmaengine: ti: k3-psil-am62: Update PSIL thread for saul. 
Correct the RX PSIL thread for sa3ul.

Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Fixes: 5ac6bfb587 ("dmaengine: ti: k3-psil: Add AM62x PSIL and PDMA data")
Link: https://lore.kernel.org/r/20220421065323.16378-1-j-choudhary@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-22 11:30:43 +05:30
Vinod Koul
e235fe3bcf dmaengine: ptdma: statify pt_tx_status 
LKP bot reports a new warning:
Warning:
drivers/dma/ptdma/ptdma-dmaengine.c:262:1: warning: no previous prototype for 'pt_tx_status' [-Wmissing-prototypes]

pt_tx_status() should be static, so declare as such.

Reported-by: kernel test robot <lkp@intel.com>
Fixes: d965068259 ("dmaengine: PTDMA: support polled mode")
Link: https://lore.kernel.org/r/20220421052407.745637-1-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-22 11:29:13 +05:30
Ben Walker
643a4a85b0 dmaengine: hidma: In hidma_prep_dma_memset treat value as a single byte 
The value parameter is a single byte, so duplicate it to the 8 byte
range that is used as the pattern.

Signed-off-by: Ben Walker <benjamin.walker@intel.com>
Cc: Sinan Kaya <okaya@kernel.org>
Link: https://lore.kernel.org/r/20220301182551.883474-5-benjamin.walker@intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-20 17:28:12 +05:30
Ben Walker
3e0c06964b dmaengine: at_xdmac: In at_xdmac_prep_dma_memset, treat value as a single byte 
The value passed in to .prep_dma_memset is to be treated as a single
byte repeating pattern.

Signed-off-by: Ben Walker <benjamin.walker@intel.com>
Cc: Ludovic Desroches <ludovic.desroches@microchip.com>
Cc: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20220301182551.883474-4-benjamin.walker@intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-20 17:28:12 +05:30
Ben Walker
ceabe10cf5 dmaengine: at_hdmac: In atc_prep_dma_memset, treat value as a single byte 
The value passed in to .prep_dma_memset is to be treated as a single
byte repeating pattern.

Signed-off-by: Ben Walker <benjamin.walker@intel.com>
Cc: Ludovic Desroches <ludovic.desroches@microchip.com>
Cc: Tudor Ambarus <tudor.ambarus@microchip.com>
Link: https://lore.kernel.org/r/20220301182551.883474-3-benjamin.walker@intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-20 17:28:12 +05:30
Ben Walker
fc44ff0ae9 dmaengine: Document dmaengine_prep_dma_memset 
Document this function to make clear the expected behavior of the
'value' parameter. It was intended to match the behavior of POSIX memset
as laid out here:

https://lore.kernel.org/dmaengine/YejrA5ZWZ3lTRO%2F1@matsya/

Signed-off-by: Ben Walker <benjamin.walker@intel.com>
Link: https://lore.kernel.org/r/20220301182551.883474-2-benjamin.walker@intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-20 17:28:12 +05:30
Dave Jiang
439b5e765a dmaengine: idxd: move wq irq enabling to after device enable 
Move the calling of request_irq() and other related irq setup code until
after the WQ is successfully enabled. This reduces the amount of
setup/teardown if the wq is not configured correctly and cannot be enabled.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/164642777730.179702.1880317757087484299.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-20 17:25:42 +05:30
Jiapeng Chong
96144c8fb3 dmaengine: tegra: Remove unused including <linux/version.h> 
Eliminate the follow versioncheck warning:

./drivers/dma/tegra186-gpc-dma.c: 21 linux/version.h not needed.

Reported-by: Abaci Robot <abaci@linux.alibaba.com>
Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com>
Link: https://lore.kernel.org/r/20220413083842.69845-1-jiapeng.chong@linux.alibaba.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-20 17:21:51 +05:30
Dave Jiang
a8facc7b98 dmaengine: add verification of DMA_INTERRUPT capability for dmatest 
Looks like I forgot to add DMA_INTERRUPT cap setting to the idxd driver and
dmatest is still working regardless of this mistake. Add an explicit check
of DMA_INTERRUPT capability for dmatest to make sure the DMA device being used
actually supports interrupt before the test is launched and also that the
driver is programmed correctly.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/164978679251.2361020.5856734256126725993.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-20 17:21:15 +05:30
Haowen Bai
e335de6ba5 dmaengine: mediatek: mtk-hsdma: use NULL instead of using plain integer as pointer 
This fixes the following sparse warnings:
drivers/dma/mediatek/mtk-hsdma.c:604:26: warning: Using plain integer
as NULL pointer

Signed-off-by: Haowen Bai <baihaowen@meizu.com>
Link: https://lore.kernel.org/r/1649750340-30777-1-git-send-email-baihaowen@meizu.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-20 17:20:02 +05:30
Haowen Bai
3dbc47a962 dmaengine: pl08x: drop the useless function 
Unneeded variable: "retval". Return "NULL" , so we have to make code clear.
better way, drop the function.

Signed-off-by: Haowen Bai <baihaowen@meizu.com>
Link: https://lore.kernel.org/r/1649726180-13133-1-git-send-email-baihaowen@meizu.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-20 17:19:09 +05:30
Dave Jiang
23084545db dmaengine: idxd: set max_xfer and max_batch for RO device 
Load the max_xfer_size and max_batch_size values from the values read from
registers to the shadow variables. This will allow the read-only device to
display the correct values for the sysfs attributes.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/164971507673.2201761.11244446608988838897.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-20 17:17:33 +05:30
Dave Jiang
4e5a4eb203 dmaengine: idxd: set DMA_INTERRUPT cap bit 
Even though idxd driver has always supported interrupt, it never actually
set the DMA_INTERRUPT cap bit. Rectify this mistake so the interrupt
capability is advertised.

Reported-by: Ben Walker <benjamin.walker@intel.com>
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/164971497859.2201379.17925303210723708961.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-20 17:17:33 +05:30
Aidan MacDonald
2128565a8d dmaengine: jz4780: set DMA maximum segment size 
Set the maximum segment size, since the hardware can do transfers larger
than the default 64 KiB returned by dma_get_max_seg_size().

The maximum segment size is limited by the 24-bit transfer count field
in DMA descriptors. The number of bytes is equal to the transfer count
times the transfer size unit, which is selected by the driver based on
the DMA buffer address and length of the transfer. The size unit can be
as small as 1 byte, so set the maximum segment size to 2^24-1 bytes to
ensure the transfer count will not overflow regardless of the size unit
selected by the driver.

Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
Link: https://lore.kernel.org/r/20220411153618.49876-1-aidanmacdonald.0x0@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-20 17:13:22 +05:30
Ilya Novikov
d965068259 dmaengine: PTDMA: support polled mode 
If the DMA_PREP_INTERRUPT flag is not provided, run in polled mode,
which significantly improves IOPS: more than twice on chunks < 4K.

Signed-off-by: Ilya Novikov <i.m.novikov@yadro.com>
Link: https://lore.kernel.org/r/20220413113733.59041-1-i.m.novikov@yadro.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-20 16:38:19 +05:30
Vinod Koul
578245307f dt-bindings: dmaengine: qcom: gpi: add compatible for sc7280 
Document the compatible for GPI DMA controller on SC7280 SoC

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220414064216.1182177-1-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-20 16:07:01 +05:30
Yunbo Yu
1d05a0bdb4 dmaengine: plx_dma: Move spin_lock_bh() to spin_lock() 
It is unnecessary to call spin_lock_bh() if you are already in a tasklet.

Signed-off-by: Yunbo Yu <yuyunbo519@gmail.com>
Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
Link: https://lore.kernel.org/r/20220418142021.1241558-1-yuyunbo519@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-20 15:59:33 +05:30
Radhey Shyam Pandey
766b540df8 dt-bindings: dmaengine: xilinx_dma: Add MCMDA channel ID index description 
MCDMA IP provides up to 16 multiple channels of data movement each on
MM2S and S2MM paths. Inline with implementation, in the binding add
description for the channel ID start index and mention that it's fixed
irrespective of the MCDMA IP configuration(number of read/write channels).

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1649939061-6675-1-git-send-email-radhey.shyam.pandey@xilinx.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-20 15:44:37 +05:30
Bjorn Andersson
d0a3ef6048 dmaengine: qcom: gpi: Add SM8350 support 
The Qualcomm SM8350 platform does, like the SM8450, provide a set of GPI
controllers with an ee-offset of 0x10000. Add this to the driver.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220412212959.2385085-1-bjorn.andersson@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-13 17:55:36 +05:30
Vinod Koul
6316572cf3 dmaengine: qcom: gpi: Add support for ee_offset 
Controller on newer SoCs like SM8450 have registers at at offset. Add
ee_offset to driver_data and add this compatible for the driver.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220406132508.1029348-3-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-13 17:54:39 +05:30
Vinod Koul
dd45d96bd9 dt-bindings: dmaengine: qcom: gpi: add compatible for sm8350/sm8350 
Add the compatible for newer qcom socs with gpi dma i.e qcom sm8350 and
sm8450.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220406132508.1029348-2-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-13 17:54:39 +05:30
Vinod Koul
94b8f0e58f dmaengine: qcom: gpi: set chain and link flag for duplex 
Newer platforms seem to have strict requirement for TRE flags which
causes transaction to timeout. This was resolved to missing chain and
link flag for duplex spi transaction.

So add these two flags.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220406132508.1029348-1-vkoul@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-13 17:54:39 +05:30
Christophe JAILLET
52126d4c03 dmaengine: Remove a useless mutex 
According to lib/idr.c,
   The IDA handles its own locking.  It is safe to call any of the IDA
   functions without synchronisation in your code.

so the 'chan_mutex' mutex can just be removed.
It is here only to protect some ida_alloc()/ida_free() calls.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Link: https://lore.kernel.org/r/7180452c1d77b039e27b6f9418e0e7d9dd33c431.1644140845.git.christophe.jaillet@wanadoo.fr
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-11 19:52:40 +05:30
Dave Jiang
2d7991fe86 dmaengine: idxd: update IAA definitions for user header 
Add additional structure definitions for Intel In-memory Analytics
Accelerator (IAA/IAX). See specification (1) for more details.

1: https://cdrdv2.intel.com/v1/dl/getContent/721858

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/164704100212.1373038.18362680016033557757.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-11 19:36:54 +05:30
Akhil R
ee17028009 dmaengine: tegra: Add tegra gpcdma driver 
Adding GPC DMA controller driver for Tegra. The driver supports dma
transfers between memory to memory, IO peripheral to memory and
memory to IO peripheral.

Co-developed-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com>
Co-developed-by: Rajesh Gumasta <rgumasta@nvidia.com>
Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com>
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20220225132044.14478-3-akhilrajeev@nvidia.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-11 19:32:24 +05:30
Akhil R
729106266a dt-bindings: dmaengine: Add doc for tegra gpcdma 
Add DT binding document for Nvidia Tegra GPCDMA controller.

Signed-off-by: Rajesh Gumasta <rgumasta@nvidia.com>
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20220225132044.14478-2-akhilrajeev@nvidia.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-11 19:32:24 +05:30
Olivier Dautricourt
cc4abaa67e dt-bindings: altr,msgdma: update my email address 
This email should now be used to contact me.

Signed-off-by: Olivier Dautricourt <olivier.dautricourt@orolia.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/dc3decf1dae172c688017bd3ada2ad2b7d060c1e.1647539776.git.olivier.dautricourt@orolia.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-11 19:22:31 +05:30
Olivier Dautricourt
745bd60094 MAINTAINERS: update my email address 
This email should now be used to contact me.

Signed-off-by: Olivier Dautricourt <olivier.dautricourt@orolia.com>
Link: https://lore.kernel.org/r/85c4174fa162bd946ccf3e08dcfc9b83cfe69b5c.1647539776.git.olivier.dautricourt@orolia.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-11 19:22:31 +05:30
Dave Jiang
81f5eb2b11 dmaengine: idxd: remove trailing white space on input str for wq name 
Add string processing with strim() in order to remove trailing white spaces
that may be input by user for the wq->name.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/164789525123.2799661.13795829125221129132.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-11 19:21:34 +05:30
Paul Kocialkowski
1f854536a8 dmaengine: Clarify cyclic transfer residue documentation 
The current documentation for the residue reported in a cyclic transfer
case mentions that the reported residue should be relative to the current
period only. However the definition of DMA_RESIDUE_GRANULARITY_SEGMENT
specifies that the residue should be updated after each period for
a cyclic transfer, which is in direct contradiction.

Moreover the pcm_dmaengine common code uses the residue relative to
the whole cyclic buffer size, not one period.

Correct the residue-related documentation to reflect this.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Link: https://lore.kernel.org/r/20220331134114.703782-1-paul.kocialkowski@bootlin.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-11 19:15:52 +05:30
Amelie Delaunay
ec834f1cc7 dmaengine: stm32-mdma: check the channel availability (secure or not) 
STM32_MDMA_CCR bit[8] is used to enable Secure Mode (SM). If this bit is
set, it means that all the channel registers are write-protected. So the
channel is not available for Linux use.

Add stm32_mdma_filter_fn() callback filter and give it to
__dma_request_chan (instead of dma_get_any_slave_channel()), to exclude the
channel if it is marked Secure.

Signed-off-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20220330103645.99969-1-amelie.delaunay@foss.st.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-11 18:58:19 +05:30
Christophe Leroy
1059893114 dmaengine: bestcomm: Prepare cleanup of powerpc's asm/prom.h 
powerpc's asm/prom.h brings some headers that it doesn't
need itself.

In order to clean it up, first add missing headers in
users of asm/prom.h

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Link: https://lore.kernel.org/r/f98acba303489bdf003e7256460696225b00702e.1648833428.git.christophe.leroy@csgroup.eu
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-11 17:43:19 +05:30
jianchunfu
9060a7a46a dmaengine: ep93xx: Remove redundant word in comment 
Remove the second 'to' which is repeated.

Signed-off-by: jianchunfu <jianchunfu@cmss.chinamobile.com>
Link: https://lore.kernel.org/r/20220403123120.7794-1-jianchunfu@cmss.chinamobile.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-11 17:31:48 +05:30
Dave Jiang
3157dd0a36 dmaengine: idxd: don't load pasid config until needed 
The driver currently programs the system pasid to the WQ preemptively when
system pasid is enabled. Given that a dwq will reprogram the pasid and
possibly a different pasid, the programming is not necessary. The pasid_en
bit can be set for swq as it does not need pasid programming but
needs the pasid_en bit. Remove system pasid programming on device config
write. Add pasid programming for kernel wq type on wq driver enable. The
char dev driver already reprograms the dwq on ->open() call so there's no
change.

Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/164935607115.1660372.6734518676950372366.stgit@djiang5-desk3.ch.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-11 17:28:58 +05:30
Lad Prabhakar
80380f89d0 dmaengine: mediatek-cqdma: Use platform_get_irq() to get the interrupt 
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static
allocation of IRQ resources in DT core code, this causes an issue
when using hierarchical interrupt domains using "interrupts" property
in the node as this bypasses the hierarchical setup and messes up the
irq chaining.

In preparation for removal of static setup of IRQ resource from DT core
code use platform_get_irq().

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220404155557.27316-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-11 16:26:53 +05:30
Lad Prabhakar
bb40bb695e dmaengine: mediatek: mtk-hsdma: Use platform_get_irq() to get the interrupt 
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static
allocation of IRQ resources in DT core code, this causes an issue
when using hierarchical interrupt domains using "interrupts" property
in the node as this bypasses the hierarchical setup and messes up the
irq chaining.

In preparation for removal of static setup of IRQ resource from DT core
code use platform_get_irq().

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220404155557.27316-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-11 16:26:53 +05:30
Lad Prabhakar
8b0c99371a dmaengine: nbpfaxi: Use platform_get_irq_optional() to get the interrupt 
platform_get_resource(pdev, IORESOURCE_IRQ, ..) relies on static
allocation of IRQ resources in DT core code, this causes an issue
when using hierarchical interrupt domains using "interrupts" property
in the node as this bypasses the hierarchical setup and messes up the
irq chaining.

In preparation for removal of static setup of IRQ resource from DT core
code use platform_get_irq_optional().

There are no non-DT users for this driver so interrupt range
(irq_res->start-irq_res->end) is no longer required and with DT we will
be sure it will be a single IRQ resource for each index.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Link: https://lore.kernel.org/r/20220404155557.27316-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-11 16:26:53 +05:30
Lad Prabhakar
448a0994cc dmaengine: sh: Kconfig: Make RZ_DMAC depend on ARCH_RZG2L 
The DMAC block is identical on Renesas RZ/G2L, RZ/G2UL and RZ/V2L SoC's, so
instead of adding dependency for each SoC's add dependency on ARCH_RZG2L.
The ARCH_RZG2L config option is already selected by ARCH_R9A07G043,
ARCH_R9A07G044 and ARCH_R9A07G054.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220406080417.14593-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-08 23:22:00 +05:30
Zong Li
e2dfce24f4 dmaengine: sf-pdma: Get number of channel by device tree 
It currently assumes that there are always four channels, it would
cause the error if there is actually less than four channels. Change
that by getting number of channel from device tree.

For backwards-compatibility, it uses the default value (i.e. 4) when
there is no 'dma-channels' information in dts.

Signed-off-by: Zong Li <zong.li@sifive.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Link: https://lore.kernel.org/r/f08a95b6582a51712c5b2c3cb859136d07bfa8b9.1648461096.git.zong.li@sifive.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-08 18:43:29 +05:30
Zong Li
06006ad29a dt-bindings: dma-engine: sifive,fu540: Add dma-channels property and modify compatible 
Add dma-channels property, then we can determine how many channels there
by device tree, rather than statically defining it in PDMA driver.
In addition, we also modify the compatible for PDMA versioning scheme.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Suggested-by: Palmer Dabbelt <palmer@rivosinc.com>
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Link: https://lore.kernel.org/r/7cc9a7b5f7e6c28fc9eb172c441b5aed2159b8a0.1648461096.git.zong.li@sifive.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2022-04-08 18:43:29 +05:30
Linus Torvalds
3123109284 Linux 5.18-rc1 v5.18-rc1 2022-04-03 14:08:21 -07:00
Linus Torvalds
09bb8856d4 Merge tag 'trace-v5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace 
Pull more tracing updates from Steven Rostedt:

 - Rename the staging files to give them some meaning. Just
   stage1,stag2,etc, does not show what they are for

 - Check for NULL from allocation in bootconfig

 - Hold event mutex for dyn_event call in user events

 - Mark user events to broken (to work on the API)

 - Remove eBPF updates from user events

 - Remove user events from uapi header to keep it from being installed.

 - Move ftrace_graph_is_dead() into inline as it is called from hot
   paths and also convert it into a static branch.

* tag 'trace-v5.18-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-trace:
  tracing: Move user_events.h temporarily out of include/uapi
  ftrace: Make ftrace_graph_is_dead() a static branch
  tracing: Set user_events to BROKEN
  tracing/user_events: Remove eBPF interfaces
  tracing/user_events: Hold event_mutex during dyn_event_add
  proc: bootconfig: Add null pointer check
  tracing: Rename the staging files for trace_events
 2022-04-03 12:26:01 -07:00
Linus Torvalds
34a53ff911 Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 
Pull clk fix from Stephen Boyd:
 "A single revert to fix a boot regression seen when clk_put() started
  dropping rate range requests. It's best to keep various systems
  booting so we'll kick this out and try again next time"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  Revert "clk: Drop the rate range on clk_put()"
 2022-04-03 12:21:14 -07:00