mirrors/linux
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-05-02 18:04:38 -04:00
Code Issues Packages Projects Releases Wiki Activity
740,972 Commits 1 Branch 928 Tags
c73a3626619018adfa2bb0fa1e64310be8e73152
Commit Graph

740972 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
Alex Deucher
c73a362661 drm/amdgpu/powerplay: fix smu7_get_memory_type for fiji 
Fiji uses a different register than other smu7 asics, but
we already have this info in the base driver so just
use that.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:12 -05:00
Harry Wentland
23b9ad21b2 Revert "drm/amd/display: disable CRTCs with NULL FB on their primary plane (V2)" 
This seems to cause flickering and lock-ups for a wide range of users.
Revert until we've found a proper fix for the flickering and lock-ups.

This reverts commit 36cc549d59.

Cc: Shirish S <shirish.s@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:12 -05:00
Harry Wentland
642ad57058 Revert "drm/amd/display: fix dereferencing possible ERR_PTR()" 
This reverts commit cd2d6c92a8.

Cc: Shirish S <shirish.s@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:11 -05:00
Alex Deucher
5eeae247d2 drm/amdgpu/gfx9: cache DB_DEBUG2 and make it available to userspace 
Userspace needs to query this value to work around a hw bug in
certain cases.

Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:11 -05:00
Christian König
5452cf44d6 drm/ttm: keep a reference to transfer pipelined BOs 
Make sure the transfered BO is never destroy before the transfer BO.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Roger He <Hongbo.He@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:11 -05:00
Rex Zhu
89a1114766 drm/amd/pp: Remove useless smu7 running state check 
Only check smc running state before start smu.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:10 -05:00
Rex Zhu
18081c2003 drm/amd/pp: Remove dead function in smu7_smumgr.c 
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:10 -05:00
Kenneth Feng
0bc8f3d29b drm/amd/powerplay: initialzie the dpm intial enabled state 
To expose the right dpm levels to the sysfs

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:09 -05:00
Kenneth Feng
564be2fc2b drm/amd/powerplay: Get more than 8 level gfxclk states 
To apply on Vega12 for more than 8 gfx dpm levels

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:09 -05:00
Kenneth Feng
61279073b1 amd/powerplay: implement the vega12_force_clock_level interface 
pp_dpm_sclk/pp_dpm_mclk in sysfs implemented to force
gfxclk/uclk dpm level for Vega12

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:09 -05:00
Rex Zhu
08ebb6e9f4 drm/amdgpu: Add APU support in vi_set_vce_clocks 
1. fix set vce clocks failed on Cz/St
   which lead 1s delay when boot up.
2. remove the workaround in vce_v3_0.c

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Shirish S <shirish.s@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
 2018-05-15 13:43:08 -05:00
Rex Zhu
819a23f83e drm/amdgpu: Add APU support in vi_set_uvd_clocks 
fix the issue set uvd clock failed on CZ/ST
which lead 1s delay when boot up.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Shirish S <shirish.s@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
 2018-05-15 13:43:08 -05:00
Rex Zhu
29ae1118d8 drm/amd/pp: Remove unnecessary forward declaration 
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:08 -05:00
Rex Zhu
45313e5f1c drm/amd/pp: Move same macro definitions to hwmgr.h 
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:07 -05:00
Shirish S
d6014e776c drm/amd/display: remove dummy is_blanked() to optimise boot time 
is_blanked() hook is a dummy one for underlay pipe, hence
when called, it loops for ~300ms at boot.

This patch removes this dummy call and adds missing checks.

Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:07 -05:00
Harry Wentland
db4b379758 drm/amd/display: Don't spam debug messages 
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:06 -05:00
Harry Wentland
2fa417324a drm/amd/display: Remove PRE_VEGA flag 
We enabled this upstream by default now and no longer need the flag.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:06 -05:00
Harry Wentland
45a2d58e84 drm/amd/display: Fix 64-bit division in hwss_edp_power_control 
Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:06 -05:00
Christian König
5422a28fe8 drm/amdgpu: fix and cleanup cpu visible VRAM handling 
The detection if a BO was placed in CPU visible VRAM was incorrect.

Fix it and merge it with the correct detection in amdgpu_ttm.c

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:05 -05:00
Christian König
f1018f50d4 drm/amdgpu: use ctx bytes_moved 
Instead of the global (inaccurate) counter.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:05 -05:00
Evan Quan
c11d8afe10 drm/amd/pp: fix the wrong readout engine clock in deep sleep 
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:04 -05:00
Evan Quan
b8a5559112 drm/amd/pp: use soc15 common macros instead of vega10 specific 
pp_soc15.h is vega10 specific. Update powerplay code to use soc15 common
macros defined in soc15_common.h.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:04 -05:00
Evan Quan
e6636ae1b7 drm/amdgpu: add MP1 and THM hw ip base reg offset 
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:04 -05:00
Rex Zhu
f73f9e35a2 drm/amd/pp: Refine pp_atomfwctrl_get_vbios_bootup_values 
In order to share pp_atomfwctrl_get_vbios_bootup_values
on asics with different BIOS_CLKID.
Not call function pp_atomfwctrl_get_clk_information_by_clkid in
pp_atomfwctrl_get_vbios_bootup_values.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:03 -05:00
Huang Rui
1bb5afd768 drm/amdgpu: fix null pointer panic with direct fw loading on gpu reset 
When system uses fw direct loading, then psp context structure won't be
initiliazed. And it is also unable to execute mode reset.

[  434.601474] amdgpu 0000:0c:00.0: GPU reset begin!
[  434.694326] amdgpu 0000:0c:00.0: GPU reset
[  434.743152] BUG: unable to handle kernel NULL pointer dereference at
0000000000000058
[  434.838474] IP: psp_gpu_reset+0xc/0x30 [amdgpu]
[  434.893532] PGD 406ed9067
[  434.893533] P4D 406ed9067
[  434.926376] PUD 400b46067
[  434.959217] PMD 0
[  435.033379] Oops: 0000 [#1] SMP
[  435.072573] Modules linked in: amdgpu(OE) chash(OE) gpu_sched(OE) ttm(OE)
drm_kms_helper(OE) drm(OE) fb_sys_fops syscopyarea sysfillrect sysimgblt
rpcsec_gss_krb5 auth_rpcgss nfsv4 nfs lockd grace fscache snd_hda_codec_realtek
snd_hda_codec_generic snd_hda_codec_hdmi snd_hda_intel snd_hda_codec
snd_hda_core snd_hwdep snd_pcm edac_mce_amd snd_seq_midi snd_seq_midi_event
kvm_amd snd_rawmidi kvm irqbypass crct10dif_pclmul crc32_pclmul snd_seq
ghash_clmulni_intel snd_seq_device pcbc snd_timer eeepc_wmi aesni_intel snd
asus_wmi aes_x86_64 sparse_keymap crypto_simd glue_helper joydev soundcore
wmi_bmof cryptd video i2c_piix4 shpchp 8250_dw i2c_designware_platform mac_hid
i2c_designware_core sunrpc parport_pc ppdev lp parport autofs4 hid_generic igb
usbhid dca ptp mxm_wmi pps_core ahci hid i2c_algo_bit
[  435.931754]  libahci wmi

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:03 -05:00
Nico Sneck
eb40c86a83 drm/radeon: add PX quirk for Asus K73TK 
With this the dGPU turns on correctly.

Signed-off-by: Nico Sneck <nicosneck@hotmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
 2018-05-15 13:43:02 -05:00
Leo (Sunpeng) Li
e405c2173e drm/amd/display: Fix memleak on input transfer function 
Input transfer function creation is now done when the plane is created.
This is done within the following change:

    Author: Anthony Koo <Anthony.Koo@amd.com>
        drm/amd/display: Have DC manage its own allocation of gamma

Therefore, we no longer need to create it when filling in the plane
attributes.

Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:02 -05:00
Leo (Sunpeng) Li
84ffa80123 drm/amd/display: Fix dim display on DCE11 
Before programming the input gamma, check that we're not using the
identity correction.

Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:02 -05:00
Anthony Koo
e43a432c01 drm/amd/display: Have DC manage its own allocation of gamma 
Creating plane will also allocate gamma and input TF
Creating stream will also allocate outputTF

Fix issue with gamma not applied
OS may call SetGamma before surface committed, so need to store
in target and apply later.

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:01 -05:00
Anthony Koo
754e367320 drm/amd/display: Fix structure initialization of hdmi_info_packet 
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:01 -05:00
Anthony Koo
28177772cb drm/amd/display: move color_transfer_func to color mod 
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:43:00 -05:00
Anthony Koo
a2e8f540c4 drm/amd/display: Refactor color module 
Remove some unnecessary TF definitions from update structures

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:42:54 -05:00
Anthony Koo
586f27a3c2 drm/amd/display: csc_transform to dc_csc_transform 
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:42:54 -05:00
Anthony Koo
5c6161162a drm/amd/display: Do not use os types 
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:42:53 -05:00
Anthony Koo
477c000ece drm/amd/display: Remove unused fields 
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:42:53 -05:00
Anthony Koo
85b2503460 drm/amd/display: Get rid of unused input_tf 
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:42:52 -05:00
Anthony Koo
0eeef69022 drm/amd/display: Updated HDR Static Metadata to directly take info packet raw 
Updated HDR Static Metadata to directly take info packet raw

Updating Infopacket does not require Passive

Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-05-15 13:42:42 -05:00
Yongqiang Sun
144de89448 drm/amd/display: dal 3.1.41 
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-04-11 13:08:10 -05:00
Roman Li
bb33b1842c drm/amd/display: Fix FBC text console corruption 
Signed-off-by: Roman Li <roman.li@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-04-11 13:08:10 -05:00
Anthony Koo
35ad2254cb drm/amd/display: csc updates require FULL update 
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-04-11 13:08:10 -05:00
Eric Bernstein
c5011872f6 drm/amd/display: Make DCN stream encoder shareable 
Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-04-11 13:08:09 -05:00
Dmytro Laktyushkin
dc002a2e4f drm/amd/display: Update scaler v_active data if interlaced 
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-04-11 13:08:09 -05:00
Yongqiang Sun
5282cbe32e drm/amd/display: Change disable backlight ramp change threshold from 0 to maximum value. 
Instead of user set brightness with range of percentage,
HLK test set brightness level with range of normal, this will result in
HLK test case set brightness from 0 to 255, DC set brightness with ramp is 0,
and disabled ramp change which will fail the HLK test.
Fix:
In case of unblank stream and turn on edp, change brightness level in
stream to 0xFFFFFFFF(actural maximum level is 0xFF), use that value as
a flag to recogonize this the case of resume from S3.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Eric Yang <eric.yang2@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-04-11 13:08:08 -05:00
Jun Lei
8f121fe281 drm/amd/display: Fill calcs date from stream src/dst if available 
We would otherwise fallback to the timing, which would always give us
identity.

Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Wesley Chalmers <Wesley.Chalmers@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-04-11 13:08:08 -05:00
Eric Yang
cf65ebeb68 drm/amd/display: fix link bw calculation for 422 and 420 encoding 
Link bw required is reduced when we have chroma subsampling.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Charlene Liu <Charlene.Liu@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-04-11 13:08:08 -05:00
Jun Lei
3dc8acad23 drm/amd/display: remove unused enum 
Signed-off-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Aric Cyr <Aric.Cyr@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-04-11 13:08:07 -05:00
Eric Bernstein
0c41891c81 drm/amd/display: Refactor stream encoder for HW review 
Move DCN1 implementation of stream encoder to new file (instead
of common dce_stream_encoder.c).
Cleanup code related to different implementation due to register
definition differences.

Signed-off-by: Eric Bernstein <eric.bernstein@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-04-11 13:08:07 -05:00
Eric Yang
1402c60517 drm/amd/display: Set all update flags when we have full update 
To prevent future optimization related bugs, just set all update
flags when we have a full update, since we know we want to reprogram
everything in that case.

Signed-off-by: Eric Yang <Eric.Yang2@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-04-11 13:08:06 -05:00
Charlene Liu
78d5d04d11 drm/amd/display: add delay between panel pwr off to on. 
As per eDP 1.4 spec, there must be at least 500ms delay
between eDP power off and on.
This change added time stamp when edp power off, which can
be used to calculate duration time when edp power on.
If duration less than 500ms, add a wait.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-04-11 13:08:06 -05:00
Harry Wentland
4c61af8afe drm/amd/display: Implement dm_get_timestamp 
We use this to ensure we wait at least 500ms in between eDP
disable/enable.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2018-04-11 13:08:06 -05:00