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Bjorn Andersson
c298af2a6d Merge branch 'icc-sm8750' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into arm64-for-6.14 
Merge SM8750 interconnect binding from topic branch, to gain access to
interconnect constants.
 2025-01-06 10:41:37 -06:00
Bjorn Andersson
05d5d3840b Merge branches '20241204-sm8750_master_clks-v3-0-1a8f31a53a86@quicinc.com' and '20250106-sm8750-dispcc-v2-1-6f42beda6317@linaro.org' into arm64-for-6.14 
Merge SM8750 gcc, tcsr and display clock bindings from topic branches,
to gain access to clock constants.
 2025-01-06 10:36:43 -06:00
Krzysztof Kozlowski
4f1a62e2b3 dt-bindings: clock: qcom,sm8550-dispcc: Add SM8750 DISPCC 
Add bindings for the Qualcomm SM8750 Display Clock Controller (DISPCC).
Bindings are similar to existing SM8550 and SM8650 (same clock inputs),
but the clock hierarchy is quite different and these are not compatible
devices.

The binding header was copied from downstream sources, so I retained
original copyrights.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250106-sm8750-dispcc-v2-1-6f42beda6317@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-01-06 10:30:00 -06:00
Taniya Das
8817c21a45 dt-bindings: clock: qcom: Document the SM8750 TCSR Clock Controller 
Add bindings documentation for the SM8750 Clock Controller.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-7-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-01-06 10:27:00 -06:00
Taniya Das
42b00f4456 dt-bindings: clock: qcom: Add SM8750 GCC 
Add device tree bindings for the global clock controller on Qualcomm
SM8750 platform.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-5-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-01-06 10:27:00 -06:00
Abel Vesa
fabdaa29f5 arm64: dts: qcom: x1e80100: Fix interconnect tags for SDHC nodes 
The CPU-to-SDHC interconnect path for the SDHC_2 needs to have the
active-only tags. The tags are missing entirely on for the SDHC_4
controller interconnect paths.

Fix all tags for both controllers.

Fixes: ffb21c1e19 ("arm64: dts: qcom: x1e80100: Describe the SDHC controllers")
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20241227-b4-x1e80100-qcp-sdhc-fixes-v1-1-cd971f7f0955@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-27 12:22:09 -06:00
Alexey Klimov
1caf6149c3 arm64: dts: qcom: qrb4210-rb2: add HDMI audio playback support 
Add sound node and dsp-related piece to enable HDMI audio
playback support on Qualcomm QRB4210 RB2 board. That is the
only sound output supported for now.

The audio playback is verified using the following commands:

amixer -c0 cset iface=MIXER,name='SEC_MI2S_RX Audio Mixer MultiMedia1' 1
aplay -D hw:0,0 /usr/share/sounds/alsa/Front_Center.wav

Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
Link: https://lore.kernel.org/r/20241112025306.712122-5-alexey.klimov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 22:26:09 -06:00
Alexey Klimov
6624d17a81 arm64: dts: qcom: sm4250: add LPASS LPI pin controller 
Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin
controller device node required for audio subsystem on Qualcomm
QRB4210 RB2. QRB4210 is based on sm4250 which has a slightly different
lpass pin controller comparing to sm6115.

While at this, also add description of lpi_i2s2 pins (active state)
required for audio playback via HDMI.

Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
Link: https://lore.kernel.org/r/20241112025306.712122-4-alexey.klimov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 22:26:09 -06:00
Alexey Klimov
4541a5f11e arm64: dts: qcom: sm6115: add LPASS LPI pin controller 
Add the Low Power Audio SubSystem Low Power Island (LPASS LPI) pin
controller device node required for audio subsystem on Qualcomm
QRB4210 RB2.

Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241112025306.712122-3-alexey.klimov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 22:26:09 -06:00
Alexey Klimov
c722e3ce27 arm64: dts: qcom: sm6115: add apr and its services 
Add apr (asynchronous packet router) node and its associated services
required to enable audio on QRB4210 RB2 platform.

Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org>
Link: https://lore.kernel.org/r/20241112025306.712122-2-alexey.klimov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 22:26:09 -06:00
Krzysztof Kozlowski
ff2b76ae68 arm64: dts: qcom: sm8650: Fix CDSP context banks unit addresses 
There is a mismatch between 'reg' property and unit address for last
there CDSP compute context banks.  Current values were taken as-is from
downstream source.  Considering that 'reg' is used by Linux driver as
SID of context bank and that least significant bytes of IOMMU value
match the 'reg', assume the unit-address is wrong and needs fixing.
This also won't have any practical impact, except adhering to Devicetree
spec.

Fixes: dae8cdb0a9 ("arm64: dts: qcom: sm8650: Add three missing fastrpc-compute-cb nodes")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20241104144204.114279-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 22:16:45 -06:00
Dmitry Baryshkov
a21fde626f arm64: dts: qcom: q[dr]u1000: move board clocks to qdu1000.dtsi file 
The QDU1000 and QRU1000 devices define XO and clocks completely in the
board files, despite qdu1000.dtsi file referencing them directly. Follow
the example of other platforms and move clock definitions to the
qdu1000.dtsi file.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-21-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 21:51:11 -06:00
Dmitry Baryshkov
55cc39c70d arm64: dts: qcom: sdm670: move board clocks to sdm670.dtsi file 
The SDM670 devices define XO and clocks completely in the
board files, despite sdm670.dtsi file referencing them directly. Follow
the example of other platforms and move clock definitions to the
sdm670.dtsi file.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-20-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 21:51:11 -06:00
Dmitry Baryshkov
aacd8c54b3 arm64: dts: qcom: sc8180x: drop extra XO clock frequencies 
sc8180x.dtsi already defines 38.4 MHz clock frequency for the XO clock.
Drop duplicate overrides from Primus and Lenovo Flex 5G DT files.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-19-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 21:51:11 -06:00
Dmitry Baryshkov
67e25a3e12 arm64: dts: qcom: x1e80100: correct sleep clock frequency 
The X1E80100 platform uses PMK8550 to provide sleep clock. According to the
documentation, that clock has 32.7645 kHz frequency. Correct the sleep
clock definition.

Fixes: af16b00578 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-18-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 21:51:11 -06:00
Dmitry Baryshkov
448db0ba6a arm64: dts: qcom: sm8650: correct sleep clock frequency 
The SM8650 platform uses PMK8550 to provide sleep clock. According to the
documentation, that clock has 32.7645 kHz frequency. Correct the sleep
clock definition.

Fixes: 6fbdb3c1fa ("arm64: dts: qcom: sm8650: add initial SM8650 MTP dts")
Fixes: a834911d50 ("arm64: dts: qcom: sm8650: add initial SM8650 QRD dts")
Fixes: 0106144102 ("arm64: dts: qcom: sm8650: add support for the SM8650-HDK board")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-17-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 21:51:11 -06:00
Dmitry Baryshkov
e59334a088 arm64: dts: qcom: sm8550: correct sleep clock frequency 
The SM8550 platform uses PMK8550 to provide sleep clock. According to the
documentation, that clock has 32.7645 kHz frequency. Correct the sleep
clock definition.

Fixes: 0b12da4e28 ("arm64: dts: qcom: add base AIM300 dtsi")
Fixes: b5e25ded27 ("arm64: dts: qcom: sm8550: add support for the SM8550-HDK board")
Fixes: 71342fb91e ("arm64: dts: qcom: Add base SM8550 MTP dts")
Fixes: d228efe884 ("arm64: dts: qcom: sm8550-qrd: add QRD8550")
Fixes: ba2c082a40 ("arm64: dts: qcom: sm8550: Add support for Samsung Galaxy Z Fold5")
Fixes: 39c596304e ("arm64: dts: qcom: Add SM8550 Xperia 1 V")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-16-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 21:51:11 -06:00
Dmitry Baryshkov
c375ff3b88 arm64: dts: qcom: sm8450: correct sleep clock frequency 
The SM8450 platform uses PMK8350 to provide sleep clock. According to the
documentation, that clock has 32.7645 kHz frequency. Correct the sleep
clock definition.

Fixes: 5188049c9b ("arm64: dts: qcom: Add base SM8450 DTSI")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-15-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 21:51:10 -06:00
Dmitry Baryshkov
f4cc8c75cf arm64: dts: qcom: sm8350: correct sleep clock frequency 
The SM8350 platform uses PMK8350 to provide sleep clock. According to the
documentation, that clock has 32.7645 kHz frequency. Correct the sleep
clock definition.

Fixes: b7e8f433a6 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-14-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 21:51:10 -06:00
Dmitry Baryshkov
75420e437e arm64: dts: qcom: sm8250: correct sleep clock frequency 
The SM8250 platform uses PM8150 to provide sleep clock. According to the
documentation, that clock has 32.7645 kHz frequency. Correct the sleep
clock definition.

Fixes: 9ff8b0591f ("arm64: dts: qcom: sm8250: use the right clock-freqency for sleep-clk")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-13-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 21:51:10 -06:00
Dmitry Baryshkov
223382c94f arm64: dts: qcom: sm6375: correct sleep clock frequency 
The SM6375 platform uses PM6125 to provide sleep clock. According to the
documentation, that clock has 32.7645 kHz frequency. Correct the sleep
clock definition.

Fixes: 59d34ca97f ("arm64: dts: qcom: Add initial device tree for SM6375")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-12-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 21:51:10 -06:00
Dmitry Baryshkov
b3c547e150 arm64: dts: qcom: sm6125: correct sleep clock frequency 
The SM6125 platform uses PM6125 to provide sleep clock. According to the
documentation, that clock has 32.7645 kHz frequency. Correct the sleep
clock definition.

Fixes: cff4bbaf2a ("arm64: dts: qcom: Add support for SM6125")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-11-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 21:51:10 -06:00
Dmitry Baryshkov
158e67cf36 arm64: dts: qcom: sm4450: correct sleep clock frequency 
The SM4450 platform uses PM4450 to provide sleep clock. According to the
documentation, that clock has 32.7645 kHz frequency. Correct the sleep
clock definition.

Fixes: 7a1fd03e74 ("arm64: dts: qcom: Adds base SM4450 DTSI")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-10-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 21:51:10 -06:00
Dmitry Baryshkov
b8021da9dd arm64: dts: qcom: sdx75: correct sleep clock frequency 
The SDX75 platform uses PMK8550 to provide sleep clock. According to the
documentation, that clock has 32.7645 kHz frequency. Correct the sleep
clock definition.

Fixes: 9181bb9399 ("arm64: dts: qcom: Add SDX75 platform and IDP board support")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-9-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 21:51:10 -06:00
Dmitry Baryshkov
f6ccdca14e arm64: dts: qcom: sc7280: correct sleep clock frequency 
The SC7280 platform uses PMK8350 to provide sleep clock. According to the
documentation, that clock has 32.7645 kHz frequency. Correct the sleep
clock definition.

Fixes: 7a1f4e7f74 ("arm64: dts: qcom: sc7280: Add basic dts/dtsi files for sc7280 soc")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-8-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 21:51:10 -06:00
Dmitry Baryshkov
7fb01ef490 arm64: dts: qcom: sar2130p: correct sleep clock frequency 
The SAR2130P platform uses PM8150 to provide sleep clock. According to the
documentation, that clock has 32.7645 kHz frequency. Correct the sleep
clock definition.

Fixes: be9115bfe5 ("arm64: dts: qcom: sar2130p: add support for SAR2130P")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-7-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 21:51:10 -06:00
Dmitry Baryshkov
298192f365 arm64: dts: qcom: qrb4210-rb2: correct sleep clock frequency 
Qualcomm RB2 board uses PM6125 to provide sleep clock. According to the
documentation, that clock has 32.7645 kHz frequency. Correct the sleep
clock definition.

Fixes: 8d58a8c0d9 ("arm64: dts: qcom: Add base qrb4210-rb2 board dts")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-6-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 21:51:10 -06:00
Dmitry Baryshkov
5546604e03 arm64: dts: qcom: q[dr]u1000: correct sleep clock frequency 
The Q[DR]U1000 platforms use PM8150 to provide sleep clock. According to
the documentation, that clock has 32.7645 kHz frequency. Correct the
sleep clock definition.

Fixes: d1f2cfe2f6 ("arm64: dts: qcom: Add base QDU1000/QRU1000 IDP DTs")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-5-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 21:51:10 -06:00
Dmitry Baryshkov
1473ff0b69 arm64: dts: qcom: qcs404: correct sleep clock frequency 
The QCS40x platforms use PMS405 to provide sleep clock. According to the
documentation, that clock has 32.7645 kHz frequency. Correct the sleep
clock definition.

Fixes: 9181bb9399 ("arm64: dts: qcom: Add SDX75 platform and IDP board support")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-4-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 21:51:09 -06:00
Dmitry Baryshkov
a4148d869d arm64: dts: qcom: msm8994: correct sleep clock frequency 
The MSM8994 platform uses PM8994/6 to provide sleep clock. According to the
documentation, that clock has 32.7645 kHz frequency. Correct the sleep
clock definition.

Fixes: feeaf56ac7 ("arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-3-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 21:51:09 -06:00
Dmitry Baryshkov
5c775f586c arm64: dts: qcom: msm8939: correct sleep clock frequency 
The MSM8939 platform uses PM8916 to provide sleep clock. According to the
documentation, that clock has 32.7645 kHz frequency. Correct the sleep
clock definition.

Fixes: 61550c6c15 ("arm64: dts: qcom: Add msm8939 SoC")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-2-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 21:51:09 -06:00
Dmitry Baryshkov
f088b92189 arm64: dts: qcom: msm8916: correct sleep clock frequency 
The MSM8916 platform uses PM8916 to provide sleep clock. According to the
documentation, that clock has 32.7645 kHz frequency. Correct the sleep
clock definition.

Fixes: f4fb6aeafa ("arm64: dts: qcom: msm8916: Add fixed rate on-board oscillators")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241224-fix-board-clocks-v3-1-e9b08fbeadd3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 21:51:09 -06:00
Dmitry Baryshkov
9fa33cbca3 arm64: dts: qcom: sm8650: correct MDSS interconnects 
SM8650 lists two interconnects for the display subsystem, mdp0-mem
(between MDP and LLCC) and mdp1-mem (between LLCC and EBI, memory).
The second interconnect is a misuse. mdpN-mem paths should be used for
several outboud MDP interconnects rather than the path between LLCC and
memory. This kind of misuse can result in bandwidth underflows, possibly
degrading picture quality as the required memory bandwidth is divided
between all mdpN-mem paths (and LLCC-EBI should not be a part of such
division).

Drop the second path and use direct MDP-EBI path for mdp0-mem until we
support separate MDP-LLCC and LLCC-EBI paths.

Fixes: 10e0246712 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes")
Cc: stable@kernel.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241026-fix-sm8x50-mdp-icc-v2-2-fd8ddf755acc@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 16:43:30 -06:00
Dmitry Baryshkov
b8591df49c arm64: dts: qcom: sm8550: correct MDSS interconnects 
SM8550 lists two interconnects for the display subsystem, mdp0-mem
(between MDP and LLCC) and mdp1-mem (between LLCC and EBI, memory).
The second interconnect is a misuse. mdpN-mem paths should be used for
several outboud MDP interconnects rather than the path between LLCC and
memory. This kind of misuse can result in bandwidth underflows, possibly
degrading picture quality as the required memory bandwidth is divided
between all mdpN-mem paths (and LLCC-EBI should not be a part of such
division).

Drop the second path and use direct MDP-EBI path for mdp0-mem until we
support separate MDP-LLCC and LLCC-EBI paths.

Fixes: d7da51db5b ("arm64: dts: qcom: sm8550: add display hardware devices")
Cc: stable@kernel.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241026-fix-sm8x50-mdp-icc-v2-1-fd8ddf755acc@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 16:43:30 -06:00
Jingyi Wang
f17a2293d0 arm64: dts: qcom: qcs8300: Add LLCC support for QCS8300 
Add Last Level Cache Controller node on the QCS8300 platform.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Link: https://lore.kernel.org/r/20241031-qcs8300_llcc-v3-3-bb56952cb83b@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 16:36:09 -06:00
Jingyi Wang
09d8a3ef91 arm64: dts: qcom: qcs8300: Add PMU support for QCS8300 
Add Performance Monitoring Unit(PMU) nodes on the QCS8300 platform.

Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241101-qcs8300_pmu-v1-1-3f3d744a3482@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 16:35:46 -06:00
Neil Armstrong
63c21d61b4 arm64: dts: qcom: sm8650: add interconnect and opp-peak-kBps for GPU 
Each GPU OPP requires a specific peak DDR bandwidth, let's add
those to each OPP and also the related interconnect path.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241217-topic-sm8x50-gpu-bw-vote-v6-7-1adaf97e7310@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 16:30:37 -06:00
Neil Armstrong
1ba4007926 arm64: dts: qcom: sm8550: add interconnect and opp-peak-kBps for GPU 
Each GPU OPP requires a specific peak DDR bandwidth, let's add
those to each OPP and also the related interconnect path.

Reviewed-by: Akhil P Oommen <quic_akhilpo@quicinc.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241217-topic-sm8x50-gpu-bw-vote-v6-6-1adaf97e7310@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 16:30:31 -06:00
Krishna Kurapati
b8993bd786 arm64: dts: qcom: qcs615-ride: Enable secondary USB controller on QCS615 Ride 
Enable secondary USB controller on QCS615 Ride platform. The secondary
USB controller is made "host", as it is a Type-A port.

Secondary USB controller of QCS615 Ride has Type-A port exposed for
connecting peripheral. The VBUS to the peripheral is provided by
TPS2549IRTERQ1 regulator connected to the port. The regulator has an
enable pin controlled by PM8150. Model it as fixed regulator and keep it
Always-On at boot, since the regulator is GPIO controlled regulator.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Co-developed-by: Song Xue <quic_songxue@quicinc.com>
Signed-off-by: Song Xue <quic_songxue@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241218-add_usb_host_mode_for_qcs615-v3-2-d9d29fe39a4b@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 16:21:12 -06:00
Krishna Kurapati
2be9609614 arm64: dts: qcom: qcs615: Add support for secondary USB node on QCS615 
Add support for secondary USB controller and its high-speed phy
on QCS615.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Co-developed-by: Song Xue <quic_songxue@quicinc.com>
Signed-off-by: Song Xue <quic_songxue@quicinc.com>
Link: https://lore.kernel.org/r/20241218-add_usb_host_mode_for_qcs615-v3-1-d9d29fe39a4b@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 16:21:12 -06:00
Luca Weiss
7fb88e0d4d arm64: dts: qcom: sm7225-fairphone-fp4: Drop extra qcom,msm-id value 
The ID 434 is for SM6350 while 459 is for SM7225. Fairphone 4 is only
SM7225, so drop the unused 434 entry.

Fixes: 4cbea66876 ("arm64: dts: qcom: sm7225: Add device tree for Fairphone 4")
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241220-fp4-msm-id-v1-1-2b75af02032a@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 15:54:18 -06:00
Pengyu Luo
1401ae5c28 arm64: dts: qcom: sc8280xp: Add Huawei Matebook E Go (sc8280xp) 
Add an initial devicetree for the Huawei Matebook E Go, which is based on
sc8280xp.

There are 3 variants, Huawei released first 2 at the same time.
Huawei Matebook E Go LTE(sc8180x), codename should be gaokun2.
Huawei Matebook E Go(sc8280xp@3.0GHz), codename is gaokun3.
Huawei Matebook E Go 2023(sc8280xp@2.69GHz).

We add support for the latter two variants.

This work started by Tianyu Gao and Xuecong Chen, they made the
devicetree based on existing work(i.e. the Lenovo X13s and the
Qualcomm CRD), it can boot with framebuffer.

Original work: https://github.com/matalama80td3l/matebook-e-go-boot-works/blob/main/dts/sc8280xp-huawei-matebook-e-go.dts

Later, I got my device, I continue their work.

Supported features:
- adsp
- bluetooth (connect issue)
- charge (with a lower power)
- framebuffer
- gpu
- keyboard (via internal USB)
- pcie devices (wifi and nvme, no modem)
- speakers and microphones
- tablet mode switch
- touchscreen
- usb
- volume key and power key

Some key features not supported yet:
- battery and charger information report (EC driver required)
- built-in display (cannot enable backlight yet)
- charging thresholds control (EC driver required)
- camera
- LID switch detection (EC driver required)
- USB Type-C altmode (EC driver required)
- USB Type-C PD (EC driver required)

I have finished the EC driver, once this series are upstreamed,
I will submit a series of patches to enable EC support.

Co-developed-by: Tianyu Gao <gty0622@gmail.com>
Signed-off-by: Tianyu Gao <gty0622@gmail.com>
Co-developed-by: Xuecong Chen <chenxuecong2009@outlook.com>
Signed-off-by: Xuecong Chen <chenxuecong2009@outlook.com>
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Link: https://lore.kernel.org/r/20241220160530.444864-4-mitltlatltl@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 15:52:07 -06:00
Pengyu Luo
f99c52954a dt-bindings: arm: qcom: Document Huawei Matebook E Go (sc8280xp) 
Add compatible for the SC8280XP-based Huawei Matebook E Go,
using its codename, gaokun3, which means it is the 3rd gen gaokun.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Link: https://lore.kernel.org/r/20241220160530.444864-2-mitltlatltl@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 15:51:36 -06:00
Barnabás Czémán
26633b5820 arm64: dts: qcom: Add Xiaomi Redmi 5A 
Add initial support for Xiaomi Redmi 5A (riva).

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
Link: https://lore.kernel.org/r/20241221-msm8917-v11-4-901a74db4805@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 15:48:23 -06:00
Barnabás Czémán
88efce82a5 dt-bindings: arm: qcom: Add Xiaomi Redmi 5A 
Document Xiaomi Remi 5A (riva).
Add qcom,msm8917 for msm-id, board-id allow-list.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
Link: https://lore.kernel.org/r/20241221-msm8917-v11-3-901a74db4805@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 15:48:23 -06:00
Otto Pflüger
7f18b1ea79 arm64: dts: qcom: Add initial support for MSM8917 
Add initial support for MSM8917 SoC.

Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de>
[reword commit, rebase, fix schema errors]
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
Link: https://lore.kernel.org/r/20241221-msm8917-v11-2-901a74db4805@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 15:48:23 -06:00
Dang Huynh
89f6e0251d arm64: dts: qcom: Add PM8937 PMIC 
The PM8937 features integrated peripherals like ADC, GPIO controller,
MPPs, PON keys and others.

Add the device tree so that any boards with this PMIC can use it.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Dang Huynh <danct12@riseup.net>
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
Link: https://lore.kernel.org/r/20241221-msm8917-v11-1-901a74db4805@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 15:48:23 -06:00
Stephan Gerhold
4861ba7cf5 arm64: dts: qcom: x1e80100-qcp: Fix USB QMP PHY supplies 
On the X1E80100 QCP, &vreg_l3e_1p2 only powers &usb_mp_qmpphy0/1
(i.e. USBSS_3 and USBSS_4). The QMP PHYs for USB_0, USB_1 and USB_2
are actually powered by &vreg_l2j_1p2.

Cc: stable@vger.kernel.org
Fixes: 20676f7819 ("arm64: dts: qcom: x1e80100-qcp: Fix USB PHYs regulators")
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20241210-x1e80100-usb-qmp-supply-fix-v1-8-0adda5d30bbd@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 15:43:37 -06:00
Stephan Gerhold
c0562f51b1 arm64: dts: qcom: x1e80100-microsoft-romulus: Fix USB QMP PHY supplies 
On the X1E80100 CRD, &vreg_l3e_1p2 only powers &usb_mp_qmpphy0/1
(i.e. USBSS_3 and USBSS_4). The QMP PHYs for USB_0, USB_1 and USB_2
are actually powered by &vreg_l2j_1p2.

Since x1e80100-microsoft-romulus mostly just mirrors the power supplies
from the x1e80100-crd device tree, assume that the fix also applies here.

Cc: stable@vger.kernel.org
Fixes: 09d77be560 ("arm64: dts: qcom: Add support for X1-based Surface Laptop 7 devices")
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20241210-x1e80100-usb-qmp-supply-fix-v1-7-0adda5d30bbd@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 15:43:37 -06:00
Stephan Gerhold
6ba8e1b824 arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Fix USB QMP PHY supplies 
On the X1E80100 CRD, &vreg_l3e_1p2 only powers &usb_mp_qmpphy0/1
(i.e. USBSS_3 and USBSS_4). The QMP PHYs for USB_0, USB_1 and USB_2
are actually powered by &vreg_l2j_1p2.

Since x1e80100-lenovo-yoga-slim7x mostly just mirrors the power supplies
from the x1e80100-crd device tree, assume that the fix also applies here.

Cc: stable@vger.kernel.org
Fixes: 45247fe17d ("arm64: dts: qcom: x1e80100: add Lenovo Thinkpad Yoga slim 7x devicetree")
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20241210-x1e80100-usb-qmp-supply-fix-v1-6-0adda5d30bbd@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-12-26 15:43:36 -06:00