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Stephen Boyd
bc060e6bb7 Merge branches 'clk-renesas', 'clk-amlogic', 'clk-allwinner' and 'clk-samsung' into clk-next 
* clk-renesas:
  clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C
  clk: renesas: r8a779h0: Add Audio clocks
  clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP
  dt-bindings: clock: rcar-gen2: Remove obsolete header files
  dt-bindings: clock: r8a7779: Remove duplicate newline
  clk: renesas: Drop "Renesas" from individual driver descriptions
  clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in comments
  clk: renesas: r8a779h0: Add VIN clocks
  dt-bindings: clock: renesas,rzg2l-cpg: Update description for #reset-cells
  clk: renesas: rcar-gen2: Use DEFINE_SPINLOCK() for static spinlock
  clk: renesas: cpg-lib: Use DEFINE_SPINLOCK() for global spinlock
  clk: renesas: r8a77970: Use common cpg_lock
  clk: renesas: r8a779h0: Add CSI-2 clocks
  clk: renesas: r8a779h0: Add ISPCS clocks

* clk-amlogic:
  clk: meson: add missing MODULE_DESCRIPTION() macros
  dt-bindings: clock: meson: a1: peripherals: support sys_pll input
  dt-bindings: clock: meson: a1: pll: introduce new syspll bindings
  clk: meson: add 'NOINIT_ENABLED' flag to eliminate init for enabled PLL
  clk: meson: c3: add c3 clock peripherals controller driver
  clk: meson: c3: add support for the C3 SoC PLL clock
  dt-bindings: clock: add Amlogic C3 peripherals clock controller
  dt-bindings: clock: add Amlogic C3 SCMI clock controller support
  dt-bindings: clock: add Amlogic C3 PLL clock controller
  dt-bindings: clock: meson: Convert axg-audio-clkc to YAML format
  clk: meson: s4: fix pwm_j_div parent clock
  clk: meson: s4: fix fixed_pll_dco clock

* clk-allwinner:
  clk: sunxi-ng r40: Constify struct regmap_config
  clk: sunxi-ng: h616: Add clock/reset for GPADC
  dt-bindings: clock: sun50i-h616-ccu: Add GPADC clocks
  clk: sunxi: Remove unused struct 'gates_data'
  clk: sunxi-ng: add missing MODULE_DESCRIPTION() macros

* clk-samsung:
  clk: samsung: gs101: mark gout_hsi2_ufs_embd_i_clk_unipro as critical
  clk: samsung: Switch to use kmemdup_array()
  clk: samsung: exynos-clkout: Remove misleading of_match_table/MODULE_DEVICE_TABLE
 2024-07-16 11:24:16 -07:00
Stephen Boyd
160d7b9fb9 Merge branches 'clk-stm', 'clk-cleanup', 'clk-kunit' and 'clk-mediatek' into clk-next 
- Add reset support to Airoha EN7581 clk driver
 - Add module description to mediatek clk drivers

* clk-stm:
  clk: stm32mp25: add security clocks
  clk: stm32mp2: use of STM32 access controller

* clk-cleanup:
  clk: mxs: Use clamp() in clk_ref_round_rate() and clk_ref_set_rate()
  clk: lpc32xx: Constify struct regmap_config
  clk: xilinx: Constify struct regmap_config
  dt-bindings: clock: sprd,sc9860-clk: convert to YAML
  dt-bindings: clock: qoriq-clock: convert to yaml format
  clk: vexpress-osc: add missing MODULE_DESCRIPTION() macro
  clk: sifive: prci: fix module autoloading
  dt-bindings: clock: milbeaut: Drop providers and consumers from example
  clk: sprd: add missing MODULE_DESCRIPTION() macro
  clk: sophgo: add missing MODULE_DESCRIPTION() macro

* clk-kunit:
  clk: disable clk gate tests for s390
  clk: test: add missing MODULE_DESCRIPTION() macros

* clk-mediatek:
  clk: en7523: fix rate divider for slic and spi clocks
  clk: en7523: Remove PCIe reset open drain configuration for EN7581
  clk: en7523: Remove pcie prepare/unpreare callbacks for EN7581 SoC
  clk: en7523: Add reset-controller support for EN7581 SoC
  dt-bindings: clock: airoha: Add reset support to EN7581 clock binding
  dt-bindings: clock: mediatek: Document reset cells for MT8188 sys
  clk: mediatek: mt8173-infracfg: Handle unallocated infracfg when module
  dt-bindings: clock: mediatek: add syscon compatible for mt7622 pciesys
  clk: mediatek: Add a module description where missing
 2024-07-16 11:24:01 -07:00
Thorsten Blum
12b02b6359 clk: mxs: Use clamp() in clk_ref_round_rate() and clk_ref_set_rate() 
Use clamp() instead of duplicating its implementation.

Signed-off-by: Thorsten Blum <thorsten.blum@toblux.com>
Link: https://lore.kernel.org/r/20240710143309.706135-2-thorsten.blum@toblux.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-07-10 13:08:59 -07:00
Javier Carrasco
38bded8154 clk: sunxi-ng r40: Constify struct regmap_config 
`sun8i_r40_ccu_regmap_config` is not modified and can be declared as
const to move its data to a read-only section.

Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com>
Link: https://lore.kernel.org/r/20240703-clk-const-regmap-v1-9-7d15a0671d6f@gmail.com
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-07-10 12:47:20 -07:00
Lorenzo Bianconi
58c53d4314 clk: en7523: fix rate divider for slic and spi clocks 
Introduce div_offset field in en_clk_desc struct in order to fix rate
divider estimation in en7523_get_div routine for slic and spi fixed
rate clocks.
Moreover, fix base_shift for crypto clock.

Fixes: 1e62731791 ("clk: en7523: Add clock driver for Airoha EN7523 SoC")
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/c491bdea05d847f1f1294b94f14725d292eb95d0.1718615934.git.lorenzo@kernel.org
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-07-08 14:43:28 -07:00
Javier Carrasco
7b34303d9d clk: lpc32xx: Constify struct regmap_config 
`lpc32xx_scb_regmap_config` is not modified and can be declared as const
to move its data to a read-only section.

Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com>
Link: https://lore.kernel.org/r/20240703-clk-const-regmap-v1-7-7d15a0671d6f@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-07-08 13:32:47 -07:00
Javier Carrasco
db8061ef91 clk: xilinx: Constify struct regmap_config 
`vcu_settings_regmap_config` is not modified and can be declared as
const to move its data to a read-only section.

Signed-off-by: Javier Carrasco <javier.carrasco.cruz@gmail.com>
Link: https://lore.kernel.org/r/20240703-clk-const-regmap-v1-10-7d15a0671d6f@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-07-08 13:32:26 -07:00
Lorenzo Bianconi
bf288bd25d clk: en7523: Remove PCIe reset open drain configuration for EN7581 
PCIe reset open drain configuration will be managed by pinctrl driver.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/43276af5f08a554b4ab2e52e8d437fff5c06a732.1719485847.git.lorenzo@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-07-08 12:08:43 -07:00
Lorenzo Bianconi
db7a4a11e8 clk: en7523: Remove pcie prepare/unpreare callbacks for EN7581 SoC 
Get rid of prepare and unpreare callbacks for PCIe clock since they can
be modeled as a reset line cosumed by the PCIe driver
(pcie-mediatek-gen3)

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/16df149975514d3030499c48fc1c64f090093595.1719485847.git.lorenzo@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-07-08 12:08:43 -07:00
Lorenzo Bianconi
e0d8ea4ed5 clk: en7523: Add reset-controller support for EN7581 SoC 
Introduce reset API support to EN7581 clock driver.

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/4f735d17e549ea53769bf5a3f50406debb879a44.1719485847.git.lorenzo@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-07-08 12:08:43 -07:00
Lorenzo Bianconi
7aa291962f dt-bindings: clock: airoha: Add reset support to EN7581 clock binding 
Introduce reset capability to EN7581 device-tree clock binding
documentation. Add reset register mapping between misc scu and pb scu
ones in order to follow the memory order. This change is not
introducing any backward compatibility issue since the EN7581 dts is not
upstream yet.

Fixes: 0a382be005 ("dt-bindings: clock: airoha: add EN7581 binding")
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
Link: https://lore.kernel.org/r/28fef3e83062d5d71e7b4be4b47583f851a15bf8.1719485847.git.lorenzo@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-07-08 12:08:43 -07:00
AngeloGioacchino Del Regno
6681afbb9c dt-bindings: clock: mediatek: Document reset cells for MT8188 sys 
The MT8188 sys clocks embed a reset controller: add #reset-cells
to the binding to allow using resets.

Fixes: 1086a5310f ("dt-bindings: clock: mediatek: Add new MT8188 clock")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20240619085322.66716-2-angelogioacchino.delregno@collabora.com
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-07-08 12:07:51 -07:00
Alper Nebi Yasak
7f294d10eb clk: mediatek: mt8173-infracfg: Handle unallocated infracfg when module 
The MT8173 infracfg clock driver does initialization in two steps, via a
CLK_OF_DECLARE_DRIVER declaration. However its early init function
doesn't get to run when it's built as a module, presumably since it's
not loaded by the time it would have been called by of_clk_init(). This
causes its second-step probe() to return -ENOMEM when trying to register
clocks, as the necessary clock_data struct isn't initialized by the
first step.

MT2701 and MT6797 clock drivers also use this mechanism, but they try to
allocate the necessary clock_data structure if missing in the second
step. Mimic that for the MT8173 infracfg clock as well to make it work
as a module.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Link: https://lore.kernel.org/r/20240612201211.91683-1-alpernebiyasak@gmail.com
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-07-08 12:06:43 -07:00
Christian Marangi
9f7809c6a8 dt-bindings: clock: mediatek: add syscon compatible for mt7622 pciesys 
Add required syscon compatible for mt7622 pciesys. This is required for
SATA interface as the regs are shared.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20240628105542.5456-2-ansuelsmth@gmail.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-07-08 12:01:46 -07:00
Stanislav Jakubek
db469084e3 dt-bindings: clock: sprd,sc9860-clk: convert to YAML 
Convert the Spreadtrum SC9860 clock bindings to DT schema.

Signed-off-by: Stanislav Jakubek <stano.jakubek@gmail.com>
Link: https://lore.kernel.org/r/ZobghvwZAyMjl4eB@standask-GA-A55M-S2HP
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-07-08 11:59:20 -07:00
Frank Li
0d796569e1 dt-bindings: clock: qoriq-clock: convert to yaml format 
Convert qoria-clock DT binding to yaml format. Split to two files
qoriq-clock.yaml and qoriq-clock-legancy.yaml.

Addtional change:
- Remove clock consumer part in example
- Fixed example dts error
- Deprecated legancy node
- fsl,b4420-clockgen and fsl,b4860-clockgen fallback to fsl,b4-clockgen.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20240701205809.1978389-1-Frank.Li@nxp.com
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-07-08 11:58:17 -07:00
Jeff Johnson
7fd3569219 clk: vexpress-osc: add missing MODULE_DESCRIPTION() macro 
With ARCH=arm64, make allmodconfig && make W=1 C=1 reports:
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/versatile/clk-vexpress-osc.o

Add the missing invocation of the MODULE_DESCRIPTION() macro.

Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com>
Link: https://lore.kernel.org/r/20240613-md-arm64-drivers-clk-versatile-v1-1-6b8a5e5e00ef@quicinc.com
Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-07-02 15:56:43 -07:00
Audra Mitchell
a6c3da03ea clk: disable clk gate tests for s390 
Currently clk-gate tests for s390 fail as the tests create a pretend
clk-gate and use a "fake_reg" to emulate the expected behavior of the
clk_gate->reg. I added some debug statements to the driver and noticed
that the reg changes after initialization to -1, which is coming from an
error coming from zpci_load(). This is likely because the test is using
fake iomem and the s390 architecture likely isn't designed to handle
that. Turn off the clk-gate tests for s390 for now as there is no clear
work around for this problem as discussed in upstream conversation [1].

[1] https://lore.kernel.org/all/301cd41e6283c12ac67fb8c0f8d5c929.sboyd@kernel.org/T/#t

Signed-off-by: Audra Mitchell <audra@redhat.com>
Link: https://lore.kernel.org/r/20240702125539.524489-1-audra@redhat.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-07-02 15:51:14 -07:00
Stephen Boyd
b1da66d28a Merge tag 'samsung-clk-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung 
Pull Samsung SoC clk drivers updates from Krzysztof Kozlowski:

 - exynos-clkout: Remove usage of of_device_id table as .of_match_table,
   because the driver is instantiated as MFD cell, not as standalone
   platform driver.  Populated .of_match_table confused people few times
   to convert the code to device_get_match_data(), which broke the
   driver.
 - Mark one of UFS clocks as critical, because having it off stops the
   system from shutdown
 - Use kmemdup_array() when applicable

* tag 'samsung-clk-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  clk: samsung: gs101: mark gout_hsi2_ufs_embd_i_clk_unipro as critical
  clk: samsung: Switch to use kmemdup_array()
  clk: samsung: exynos-clkout: Remove misleading of_match_table/MODULE_DEVICE_TABLE
 2024-07-02 12:40:30 -07:00
Stephen Boyd
c181b16fcb Merge tag 'sunxi-clk-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner 
Pull Allwinner SoC clk driver updates from Chen-Yu Tsai:

- Remove unused 'struct gates_data' from old sunxi driver library
- Add missing MODULE_DESCRIPTION() macros for sunxi-ng drivers
- Add GPADC clock and reset for H616

* tag 'sunxi-clk-for-6.11' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: h616: Add clock/reset for GPADC
  dt-bindings: clock: sun50i-h616-ccu: Add GPADC clocks
  clk: sunxi: Remove unused struct 'gates_data'
  clk: sunxi-ng: add missing MODULE_DESCRIPTION() macros
 2024-07-01 13:21:07 -07:00
Stephen Boyd
d424c029af Merge tag 'clk-meson-v6.11-1' of https://github.com/BayLibre/clk-meson into clk-amlogic 
Pull Amlogic clock driver updates from Jerome Brunet:

 - Minor S4 clock fixes
 - DT bindings Yaml conversion of the AXG audio controller
 - C3 clock controllers support
 - Flag added to skip init of already enabled PLLs and avoid relocking
 - A1 DT bindings updates for system pll support
 - Add missing MODULE_DESCRIPTION where necessary.

* tag 'clk-meson-v6.11-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: add missing MODULE_DESCRIPTION() macros
  dt-bindings: clock: meson: a1: peripherals: support sys_pll input
  dt-bindings: clock: meson: a1: pll: introduce new syspll bindings
  clk: meson: add 'NOINIT_ENABLED' flag to eliminate init for enabled PLL
  clk: meson: c3: add c3 clock peripherals controller driver
  clk: meson: c3: add support for the C3 SoC PLL clock
  dt-bindings: clock: add Amlogic C3 peripherals clock controller
  dt-bindings: clock: add Amlogic C3 SCMI clock controller support
  dt-bindings: clock: add Amlogic C3 PLL clock controller
  dt-bindings: clock: meson: Convert axg-audio-clkc to YAML format
  clk: meson: s4: fix pwm_j_div parent clock
  clk: meson: s4: fix fixed_pll_dco clock
 2024-07-01 13:12:24 -07:00
Stephen Boyd
e96b042098 Merge tag 'renesas-clk-for-v6.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas 
Pull Renesas clk driver updates from Geert Uytterhoeven:

 - Remove obsolete clock DT binding header files
 - Add Battery Backup (VBATTB) and I2C clocks, resets, and power
   domains on RZ/G3S
 - Add audio clocks on R-Car V4M
 - Add video capture (ISPCS, CSI-2, VIN) clocks on R-Car V4M
 - Miscellaneous fixes and improvements

* tag 'renesas-clk-for-v6.11-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C
  clk: renesas: r8a779h0: Add Audio clocks
  clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP
  dt-bindings: clock: rcar-gen2: Remove obsolete header files
  dt-bindings: clock: r8a7779: Remove duplicate newline
  clk: renesas: Drop "Renesas" from individual driver descriptions
  clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in comments
  clk: renesas: r8a779h0: Add VIN clocks
  dt-bindings: clock: renesas,rzg2l-cpg: Update description for #reset-cells
  clk: renesas: rcar-gen2: Use DEFINE_SPINLOCK() for static spinlock
  clk: renesas: cpg-lib: Use DEFINE_SPINLOCK() for global spinlock
  clk: renesas: r8a77970: Use common cpg_lock
  clk: renesas: r8a779h0: Add CSI-2 clocks
  clk: renesas: r8a779h0: Add ISPCS clocks
 2024-07-01 13:08:15 -07:00
Peter Griffin
e61f400d6c clk: samsung: gs101: mark gout_hsi2_ufs_embd_i_clk_unipro as critical 
The system hangs on poweroff when this UFS clock is turned off, meaning
the system never powers down. For the moment mark the clock as critical.

Reviewed-by: Will McVicker <willmcvicker@google.com>
Tested-by: Will McVicker <willmcvicker@google.com>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20240628223506.1237523-5-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2024-07-01 10:15:30 +02:00
Claudiu Beznea
c7e58843d1 clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C 
Add clock, reset and power domain support for the I2C channels available
on the Renesas RZ/G3S SoC.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240625121358.590547-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-06-27 18:17:13 +02:00
Kuninori Morimoto
1f5ed3ae02 clk: renesas: r8a779h0: Add Audio clocks 
Add module clocks for the Audio (SSI/SSIU) blocks on the Renesas R-Car
V4M (R8A779H0) SoC.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/87h6djkxf2.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-06-27 18:17:00 +02:00
Claudiu Beznea
c8bd9bd644 clk: renesas: r9a08g045: Add clock, reset and power domain support for the VBATTB IP 
The Renesas RZ/G3S SoC has an IP named Battery Backup Function (VBATTB)
that generates the RTC clock. Add clock, reset and power domain support
for it.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240614071932.1014067-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-06-27 18:16:39 +02:00
Geert Uytterhoeven
d6c5fc9add dt-bindings: clock: rcar-gen2: Remove obsolete header files 
The clock definitions in <dt-bindings/clock/r8a779?-clock.h> were
superseded by those in <dt-bindings/clock/r8a779?-cpg-mssr.h> a long
time ago.

The last DTS user of these files was removed in commit 362b334b17
("ARM: dts: r8a7791: Convert to new CPG/MSSR bindings") in v4.15.
Driver support for the old bindings was removed in commit
58256143cf ("clk: renesas: Remove R-Car Gen2 legacy DT clock
support") in v5.5, so there is no point to keep on carrying these.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/d4abb688d666be35e99577a25b16958cbb4c3c98.1718796005.git.geert+renesas@glider.be
 2024-06-24 15:51:07 +02:00
Marek Vasut
c5d1e53040 dt-bindings: clock: r8a7779: Remove duplicate newline 
Drop duplicate newline. No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240616160038.45937-1-marek.vasut+renesas@mailbox.org
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-06-24 15:51:07 +02:00
Geert Uytterhoeven
ebae969d2f clk: renesas: Drop "Renesas" from individual driver descriptions 
All configuration options are under the big "Renesas SoC clock support"
umbrella, so there is no reason to repeat this for each driver.
Hence drop "Renesas" from the few that do.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/185323de4d38b9b599775c1b64ce4171551b98d5.1718177124.git.geert+renesas@glider.be
 2024-06-24 15:51:06 +02:00
Geert Uytterhoeven
362951fef4 clk: renesas: r8a779h0: Fix PLL2/PLL4 multipliers in comments 
The multipliers for PLL2 and PLL4 as listed in the comments for
the cpg_pll_configs[] array are incorrect.  Fix them.

Note that the actual values in the tables were correct.

Fixes: f077cab34d ("clk: renesas: cpg-mssr: Add support for R-Car V4M")
Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/07126b55807c1596422c9547e72f0a032487da1e.1718177076.git.geert+renesas@glider.be
 2024-06-24 15:51:04 +02:00
Chris Morgan
002cf0dfa2 clk: sunxi-ng: h616: Add clock/reset for GPADC 
Add the GPADC required clock and reset which is used for the onboard
GPADC.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Link: https://lore.kernel.org/r/20240605172049.231108-3-macroalpha82@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
 2024-06-22 20:09:20 +08:00
Chen-Yu Tsai
29f1841185 Merge branch 'sunxi/shared-clk-ids-for-6.11' into sunxi/clk-for-6.11 2024-06-22 20:07:02 +08:00
Chris Morgan
532857c2a7 dt-bindings: clock: sun50i-h616-ccu: Add GPADC clocks 
Add the required clock bindings for the GPADC.

Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240605172049.231108-2-macroalpha82@gmail.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
 2024-06-22 20:06:26 +08:00
Andy Shevchenko
7666718892 clk: samsung: Switch to use kmemdup_array() 
Let the kememdup_array() take care about multiplication and possible
overflows.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20240606161028.2986587-4-andriy.shevchenko@linux.intel.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 2024-06-16 09:20:48 +02:00
Jerome Brunet
befe87380e clk: meson: add missing MODULE_DESCRIPTION() macros 
Add the missing MODULE_DESCRIPTION() in the Amlogic clock modules missing
it.

Reported-by: Jeff Johnson <quic_jjohnson@quicinc.com>
Closes: https://lore.kernel.org/linux-clk/964210f1-671f-4ecc-bdb7-3cf53089c327@quicinc.com
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240611133512.341817-1-jbrunet@baylibre.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
 2024-06-14 09:29:41 +02:00
Niklas Söderlund
f92d44a00b clk: renesas: r8a779h0: Add VIN clocks 
Add the VIN module clocks, which are used by the VIN modules on the
Renesas R-Car V4M (R8A779H0) SoC.

Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240606170858.1694652-1-niklas.soderlund+renesas@ragnatech.se
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-06-11 09:36:27 +02:00
Lad Prabhakar
d8abcb7377 dt-bindings: clock: renesas,rzg2l-cpg: Update description for #reset-cells 
For the RZ/G2L and similar SoCs, the reset specifier is the reset number
and not the module number. Reflect this in the description for the
'#reset-cells' property.

Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240606161047.663833-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2024-06-11 09:36:15 +02:00
Jerome Brunet
f34da56094 Merge branch 'v6.11/bindings' into v6.11/drivers 
* v6.11/bindings:
  dt-bindings: clock: meson: a1: peripherals: support sys_pll input
  dt-bindings: clock: meson: a1: pll: introduce new syspll bindings
 2024-06-10 12:18:15 +02:00
Dmitry Rokosov
41056416ed dt-bindings: clock: meson: a1: peripherals: support sys_pll input 
The 'sys_pll' input is an optional clock that can be used to generate
'sys_pll_div16', which serves as one of the sources for the GEN clock.

Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240515185103.20256-5-ddrokosov@salutedevices.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
 2024-06-10 12:16:45 +02:00
Dmitry Rokosov
96f3b97873 dt-bindings: clock: meson: a1: pll: introduce new syspll bindings 
The 'syspll' PLL is a general-purpose PLL designed specifically for the
CPU clock. It is capable of producing output frequencies within the
range of 768MHz to 1536MHz.

The 'syspll_in' source clock is an optional parent connection from the
peripherals clock controller.

Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240515185103.20256-3-ddrokosov@salutedevices.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
 2024-06-10 12:16:45 +02:00
Dmitry Rokosov
d4c83ac16c clk: meson: add 'NOINIT_ENABLED' flag to eliminate init for enabled PLL 
When dealing with certain PLLs, it is necessary to avoid modifying them
if they have already been initialized by lower levels. For instance, in
the A1 SoC Family, the sys_pll is enabled as the parent for the cpuclk,
and it cannot be disabled during the initialization sequence. Therefore,
initialization phase must be skipped.

Signed-off-by: Dmitry Rokosov <ddrokosov@salutedevices.com>
Link: https://lore.kernel.org/r/20240515185103.20256-2-ddrokosov@salutedevices.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
 2024-06-10 12:16:01 +02:00
Geert Uytterhoeven
2092760681 clk: renesas: rcar-gen2: Use DEFINE_SPINLOCK() for static spinlock 
A static spinlock can be initialized automatically with
DEFINE_SPINLOCK() rather than explicitly calling spin_lock_init().

Suggested-by: Ye Bin <yebin10@huawei.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/8da2c908f00043f05f7e26e3c26400aea0cfe8bc.1716975021.git.geert+renesas@glider.be
 2024-06-07 14:10:15 +02:00
Geert Uytterhoeven
3b2f834dd3 clk: renesas: cpg-lib: Use DEFINE_SPINLOCK() for global spinlock 
A global spinlock can be initialized automatically with
DEFINE_SPINLOCK() rather than explicitly calling spin_lock_init().

Suggested-by: Ye Bin <yebin10@huawei.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/9073a6bfb7791e492156331fa8a0ea87a7c7cef6.1716975021.git.geert+renesas@glider.be
 2024-06-07 14:09:59 +02:00
Geert Uytterhoeven
c001f9c9bc clk: renesas: r8a77970: Use common cpg_lock 
R-Car Gen3 Socs use the common CPG/MSSR library functions in
rcar-cpg-lib.c, so the R-Car V3M sub-driver can use the common cpg_lock
instead of a driver-private lock.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/0cd9b5ffbe986bd7dc4ffb3f13492123432ee2e1.1716975021.git.geert+renesas@glider.be
 2024-06-07 14:09:34 +02:00
Krzysztof Kozlowski
6ea810cfb8 clk: sifive: prci: fix module autoloading 
Add MODULE_DEVICE_TABLE(), so modules could be properly autoloaded
based on the alias from of_device_id table.  Clocks are considered core
components, so usually they are built-in, however these can be built and
used as modules on some generic kernel.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Link: https://lore.kernel.org/r/20240604130531.170371-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2024-06-04 11:37:16 -07:00
Dr. David Alan Gilbert
95fd34a859 clk: sunxi: Remove unused struct 'gates_data' 
'gates_data' (and it's associated define) are unused since
commit ee38b2698a ("clk: sunxi: Add a simple gates driver").
Remove them.

Signed-off-by: Dr. David Alan Gilbert <linux@treblig.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20240509230516.86023-1-linux@treblig.org
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
 2024-06-04 20:58:05 +08:00
Jeff Johnson
4e7134faf3 clk: sunxi-ng: add missing MODULE_DESCRIPTION() macros 
make allmodconfig && make W=1 C=1 reports:
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sunxi-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/suniv-f1c100s-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun20i-d1-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun20i-d1-r-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun50i-a64-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun50i-a100-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun50i-a100-r-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun50i-h6-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun50i-h6-r-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun50i-h616-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun4i-a10-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun6i-a31-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun6i-rtc-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun8i-a23-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun8i-a33-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun8i-a83t-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun8i-h3-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun8i-r40-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun8i-v3s-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun8i-de2-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun8i-r-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun9i-a80-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun9i-a80-de-ccu.o
WARNING: modpost: missing MODULE_DESCRIPTION() in drivers/clk/sunxi-ng/sun9i-a80-usb-ccu.o

Add the missing invocations of the MODULE_DESCRIPTION() macro.

Signed-off-by: Jeff Johnson <quic_jjohnson@quicinc.com>
Link: https://lore.kernel.org/r/20240603-md-drivers-clk-sunxi-ng-v1-1-c44a4c22d544@quicinc.com
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
 2024-06-04 20:46:43 +08:00
Xianwei Zhao
f06ac3ed04 clk: meson: c3: add c3 clock peripherals controller driver 
Add the C3 peripherals clock controller driver in the C3 SoC family.

[jbrunet: fix Kconfig select order and probe function name]
Co-developed-by: Chuan Liu <chuan.liu@amlogic.com>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Link: https://lore.kernel.org/r/20240522082727.3029656-6-xianwei.zhao@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
 2024-06-04 10:38:32 +02:00
Xianwei Zhao
8a9a129dc5 clk: meson: c3: add support for the C3 SoC PLL clock 
Add the C3 PLL clock controller driver for the Amlogic C3 SoC family.

[jbrunet: fixed probe function name]
Co-developed-by: Chuan Liu <chuan.liu@amlogic.com>
Signed-off-by: Chuan Liu <chuan.liu@amlogic.com>
Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com>
Link: https://lore.kernel.org/r/20240522082727.3029656-5-xianwei.zhao@amlogic.com
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
 2024-06-04 10:38:16 +02:00
Jerome Brunet
d7583cde8c Merge branch 'v6.11/bindings' into v6.11/drivers 
* v6.11/bindings:
  dt-bindings: clock: add Amlogic C3 peripherals clock controller
  dt-bindings: clock: add Amlogic C3 SCMI clock controller support
  dt-bindings: clock: add Amlogic C3 PLL clock controller
 2024-06-04 10:28:21 +02:00