Commit Graph

75871 Commits

Author SHA1 Message Date
David Lechner
6ade82946f iio: ABI: use Y consistently as channel number
Change X to Y when referring to channel number in the ABI documentation.
There were only a few cases using X (and one using Z). By far, most
documented attributes are using Y for the channel number placeholder.
For consistency, we should follow the same convention throughout.

Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://patch.msgid.link/20241216-doc-iio-use-voltagey-consistently-v1-1-9e34a72133bc@baylibre.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2024-12-28 14:28:13 +00:00
Per-Daniel Olsson
0c6db4506a iio: light: Add support for TI OPT4060 color sensor
Add support for Texas Instruments OPT4060 RGBW Color sensor.

Signed-off-by: Per-Daniel Olsson <perdaniel.olsson@axis.com>
Link: https://patch.msgid.link/20241218104836.2784523-3-perdaniel.olsson@axis.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2024-12-28 14:28:13 +00:00
Per-Daniel Olsson
8354dc8924 dt-bindings: iio: light: Document TI OPT4060 RGBW sensor
Add devicetree bindings for the OPT4060 RGBW color sensor.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Per-Daniel Olsson <perdaniel.olsson@axis.com>
Link: https://patch.msgid.link/20241218104836.2784523-2-perdaniel.olsson@axis.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2024-12-28 14:28:13 +00:00
Vasileios Amoiridis
4358b76480 dt-bindings: iio: pressure: bmp085: Add SPI interface
The BMP{2,3,5}80 and BME280 devices have an SPI interface, so include it
in the device-tree.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Vasileios Amoiridis <vassilisamir@gmail.com>
Link: https://patch.msgid.link/20241209233845.29539-2-vassilisamir@gmail.com
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2024-12-28 14:28:13 +00:00
Kanchana P Sridhar
4ebd9a5ca4 crypto: iaa - Fix IAA disabling that occurs when sync_mode is set to 'async'
With the latest mm-unstable, setting the iaa_crypto sync_mode to 'async'
causes crypto testmgr.c test_acomp() failure and dmesg call traces, and
zswap being unable to use 'deflate-iaa' as a compressor:

echo async > /sys/bus/dsa/drivers/crypto/sync_mode

[  255.271030] zswap: compressor deflate-iaa not available
[  369.960673] INFO: task cryptomgr_test:4889 blocked for more than 122 seconds.
[  369.970127]       Not tainted 6.13.0-rc1-mm-unstable-12-16-2024+ #324
[  369.977411] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message.
[  369.986246] task:cryptomgr_test  state:D stack:0     pid:4889  tgid:4889  ppid:2      flags:0x00004000
[  369.986253] Call Trace:
[  369.986256]  <TASK>
[  369.986260]  __schedule+0x45c/0xfa0
[  369.986273]  schedule+0x2e/0xb0
[  369.986277]  schedule_timeout+0xe7/0x100
[  369.986284]  ? __prepare_to_swait+0x4e/0x70
[  369.986290]  wait_for_completion+0x8d/0x120
[  369.986293]  test_acomp+0x284/0x670
[  369.986305]  ? __pfx_cryptomgr_test+0x10/0x10
[  369.986312]  alg_test_comp+0x263/0x440
[  369.986315]  ? sched_balance_newidle+0x259/0x430
[  369.986320]  ? __pfx_cryptomgr_test+0x10/0x10
[  369.986323]  alg_test.part.27+0x103/0x410
[  369.986326]  ? __schedule+0x464/0xfa0
[  369.986330]  ? __pfx_cryptomgr_test+0x10/0x10
[  369.986333]  cryptomgr_test+0x20/0x40
[  369.986336]  kthread+0xda/0x110
[  369.986344]  ? __pfx_kthread+0x10/0x10
[  369.986346]  ret_from_fork+0x2d/0x40
[  369.986355]  ? __pfx_kthread+0x10/0x10
[  369.986358]  ret_from_fork_asm+0x1a/0x30
[  369.986365]  </TASK>

This happens because the only async polling without interrupts that
iaa_crypto currently implements is with the 'sync' mode. With 'async',
iaa_crypto calls to compress/decompress submit the descriptor and return
-EINPROGRESS, without any mechanism in the driver to poll for
completions. Hence callers such as test_acomp() in crypto/testmgr.c or
zswap, that wrap the calls to crypto_acomp_compress() and
crypto_acomp_decompress() in synchronous wrappers, will block
indefinitely. Even before zswap can notice this problem, the crypto
testmgr.c's test_acomp() will fail and prevent registration of
"deflate-iaa" as a valid crypto acomp algorithm, thereby disallowing the
use of "deflate-iaa" as a zswap compress (zswap will fall-back to the
default compressor in this case).

To fix this issue, this patch modifies the iaa_crypto sync_mode set
function to treat 'async' equivalent to 'sync', so that the correct and
only supported driver async polling without interrupts implementation is
enabled, and zswap can use 'deflate-iaa' as the compressor.

Hence, with this patch, this is what will happen:

echo async > /sys/bus/dsa/drivers/crypto/sync_mode
cat /sys/bus/dsa/drivers/crypto/sync_mode
sync

There are no crypto/testmgr.c test_acomp() errors, no call traces and zswap
can use 'deflate-iaa' without any errors. The iaa_crypto documentation has
also been updated to mention this caveat with 'async' and what to expect
with this fix.

True iaa_crypto async polling without interrupts is enabled in patch
"crypto: iaa - Implement batch_compress(), batch_decompress() API in
iaa_crypto." [1] which is under review as part of the "zswap IAA compress
batching" patch-series [2]. Until this is merged, we would appreciate it if
this current patch can be considered for a hotfix.

[1]: https://patchwork.kernel.org/project/linux-mm/patch/20241221063119.29140-5-kanchana.p.sridhar@intel.com/
[2]: https://patchwork.kernel.org/project/linux-mm/list/?series=920084

Fixes: 09646c98d ("crypto: iaa - Add irq support for the crypto async interface")
Signed-off-by: Kanchana P Sridhar <kanchana.p.sridhar@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2024-12-28 19:49:23 +08:00
Matthieu Baerts (NGI0)
4f363fe9f6 netlink: specs: mptcp: fix missing doc
Two operations didn't have a small description. It looks like something
that has been missed in the original commit introducing this file.

Replace the two "todo" by a small and simple description: Create/Destroy
subflow.

While at it, also uniform the capital letters, avoid double spaces, and
fix the "announce" event description: a new "address" has been
announced, not a new "subflow".

Reviewed-by: Geliang Tang <geliang@kernel.org>
Signed-off-by: Matthieu Baerts (NGI0) <matttbe@kernel.org>
Link: https://patch.msgid.link/20241221-net-mptcp-netlink-specs-pm-doc-fixes-v2-3-e54f2db3f844@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-12-27 11:16:21 -08:00
Matthieu Baerts (NGI0)
bea87657b5 netlink: specs: mptcp: clearly mention attributes
The rendered version of the MPTCP events [1] looked strange, because the
whole content of the 'doc' was displayed in the same block.

It was then not clear that the first words, not even ended by a period,
were the attributes that are defined when such events are emitted. These
attributes have now been moved to the end, prefixed by 'Attributes:' and
ended with a period. Note that '>-' has been added after 'doc:' to allow
':' in the text below.

The documentation in the UAPI header has been auto-generated by:

  ./tools/net/ynl/ynl-regen.sh

Link: https://docs.kernel.org/networking/netlink_spec/mptcp_pm.html#event-type [1]
Reviewed-by: Geliang Tang <geliang@kernel.org>
Signed-off-by: Matthieu Baerts (NGI0) <matttbe@kernel.org>
Link: https://patch.msgid.link/20241221-net-mptcp-netlink-specs-pm-doc-fixes-v2-2-e54f2db3f844@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-12-27 11:16:21 -08:00
Matthieu Baerts (NGI0)
6b830c6a02 netlink: specs: mptcp: add missing 'server-side' attr
This attribute is added with the 'created' and 'established' events, but
the documentation didn't mention it.

The documentation in the UAPI header has been auto-generated by:

  ./tools/net/ynl/ynl-regen.sh

Reviewed-by: Geliang Tang <geliang@kernel.org>
Signed-off-by: Matthieu Baerts (NGI0) <matttbe@kernel.org>
Link: https://patch.msgid.link/20241221-net-mptcp-netlink-specs-pm-doc-fixes-v2-1-e54f2db3f844@kernel.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-12-27 11:16:21 -08:00
Kever Yang
1dc7fd41e8 dt-bindings: pinctrl: Add rk3562 pinctrl support
Add the compatible string for the rk3562 SoC.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/20241224093522.3815562-1-kever.yang@rock-chips.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-12-27 17:11:18 +01:00
Krishna Kurapati
f097a36ef8 dt-bindings: usb: qcom,dwc3: Add QCS615 to USB DWC3 bindings
Update dt-bindings to add primary controller of QCS615 to USB
DWC3 controller list.

Although this controller has a QUSB2 Phy, it belongs to a
generation of SoCs like SDM670/SDM845/SM6350 where DP/DM is
used for wakeup instead of qusb2_phy interrupt.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241224084621.4139021-2-krishna.kurapati@oss.qualcomm.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-12-27 13:09:50 +01:00
Gordon Ou
63f0abcb47 USB: usbip: Update USB/IP OP_REP_IMPORT documentation.
This is to correct the mistaken byte offset of the field bDeviceClass in
OP_REP_IMPORT documentation. The previous field bcdDevice has length 2 and
the offset for bDeviceClass should be 0x138 + 2 = 0x13A instead of 0x139.
Offsets for subsequent fields are also affected and fixed in this patch.

Signed-off-by: Gordon Ou <gordon.xwj@gmail.com>
Reviewed-by: Shuah Khan <skhan@linuxfoundation.org>
Link: https://lore.kernel.org/r/20241224062336.63215-1-gordon.xwj@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-12-27 13:07:22 +01:00
Frank Wunderlich
e4ee0acff5 dt-bindings: pinctrl: add binding for MT7988 SoC
This adds bindings for MT7988 pinctrl driver.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/20241217085435.9586-4-linux@fw-web.de
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2024-12-27 09:22:05 +01:00
Pengyu Luo
f99c52954a dt-bindings: arm: qcom: Document Huawei Matebook E Go (sc8280xp)
Add compatible for the SC8280XP-based Huawei Matebook E Go,
using its codename, gaokun3, which means it is the 3rd gen gaokun.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Link: https://lore.kernel.org/r/20241220160530.444864-2-mitltlatltl@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26 15:51:36 -06:00
Barnabás Czémán
88efce82a5 dt-bindings: arm: qcom: Add Xiaomi Redmi 5A
Document Xiaomi Remi 5A (riva).
Add qcom,msm8917 for msm-id, board-id allow-list.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Barnabás Czémán <barnabas.czeman@mainlining.org>
Link: https://lore.kernel.org/r/20241221-msm8917-v11-3-901a74db4805@mainlining.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26 15:48:23 -06:00
Jens Glathe
4e65a06422 dt-bindings: arm: qcom: Add Microsoft Windows Dev Kit 2023
Add compatible values for the Microsoft Windows Dev Kit (WDK2023)
with its codename "blackrock". The Dev kit is a small desktop box
based on the mainboard of the Surface pro 9 5G, intended for
developers to test/build arm64-based Windows software.
Link: https://learn.microsoft.com/en-us/windows/arm/dev-kit/

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz>
Link: https://lore.kernel.org/r/20241202-jg-blackrock-for-upstream-v9-1-385bb46ca122@oldschoolsolutions.biz
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26 15:26:44 -06:00
Jens Glathe
6ba121febf dt-bindings: arm: qcom: Add HP Omnibook X 14
Add compatible values for the HP Omnibook X Laptop 14-fe0750ng,
using "hp,omnibook-x14"

The laptop is based on the Snapdragon X Elite (x1e80100) SoC.

PDF link: https://www8.hp.com/h20195/V2/GetPDF.aspx/c08989140

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz>
Link: https://lore.kernel.org/r/20241202-hp-omnibook-x14-v3-1-0fcd96483723@oldschoolsolutions.biz
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-26 15:23:40 -06:00
MD Danish Anwar
f7ed5ae30c dt-bindings: soc: ti: pruss: Add clocks for ICSSG
The ICSSG module has 7 clocks for each instance.

These clocks are ICSSG0_CORE_CLK, ICSSG0_IEP_CLK, ICSSG0_ICLK,
ICSSG0_UART_CLK, RGMII_MHZ_250_CLK, RGMII_MHZ_50_CLK and RGMII_MHZ_5_CLK
These clocks are described in AM64x TRM Section 6.4.3 Table 6-398.

Add these clocks to the dt binding of ICSSG.

Link: https://www.ti.com/lit/pdf/spruim2 (AM64x TRM)
Signed-off-by: MD Danish Anwar <danishanwar@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241113110955.3876045-2-danishanwar@ti.com
Signed-off-by: Nishanth Menon <nm@ti.com>
2024-12-26 14:00:54 -06:00
Linus Torvalds
d6ef8b40d0 Merge tag 'sound-6.13-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound
Pull sound fixes from Takashi Iwai:
 "A collection of small fixes. Nothing really stands out, fortunately.

   - Follow-up fixes for the new compress offload API extension

   - A few ASoC SOF, AMD and Mediatek quirks and fixes

   - A regression fix in legacy SH driver cleanup

   - Fix DMA mapping error handling in the helper code

   - Fix kselftest dependency"

* tag 'sound-6.13-rc5' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound:
  ALSA: sh: Fix wrong argument order for copy_from_iter()
  selftests/alsa: Fix circular dependency involving global-timer
  ALSA: memalloc: prefer dma_mapping_error() over explicit address checking
  ALSA: compress_offload: improve file descriptors installation for dma-buf
  ALSA: compress_offload: use safe list iteration in snd_compr_task_seq()
  ALSA: compress_offload: avoid 64-bit get_user()
  ALSA: compress_offload: import DMA_BUF namespace
  ASoC: mediatek: disable buffer pre-allocation
  ASoC: rt722: add delay time to wait for the calibration procedure
  ASoC: SOF: Intel: hda-dai: Do not release the link DMA on STOP
  ASoC: dt-bindings: realtek,rt5645: Fix CPVDD voltage comment
  ASoC: Intel: sof_sdw: Fix DMI match for Lenovo 21QA and 21QB
  ASoC: Intel: sof_sdw: Fix DMI match for Lenovo 21Q6 and 21Q7
  ASoC: amd: ps: Fix for enabling DMIC on acp63 platform via _DSD entry
2024-12-26 10:49:02 -08:00
Masami Hiramatsu (Google)
54b6b4a3d4 Documentation: probes: Update fprobe on function-graph tracer
Update fprobe documentation for the new fprobe on function-graph
tracer. This includes some bahvior changes and pt_regs to
ftrace_regs interface change.

Cc: Alexei Starovoitov <alexei.starovoitov@gmail.com>
Cc: Florent Revest <revest@chromium.org>
Cc: Martin KaFai Lau <martin.lau@linux.dev>
Cc: bpf <bpf@vger.kernel.org>
Cc: Alexei Starovoitov <ast@kernel.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Alan Maguire <alan.maguire@oracle.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/173519010442.391279.10732749889346824783.stgit@devnote2
Signed-off-by: Masami Hiramatsu (Google) <mhiramat@kernel.org>
Signed-off-by: Steven Rostedt (Google) <rostedt@goodmis.org>
2024-12-26 10:50:06 -05:00
Taniya Das
9446506226 dt-bindings: clock: qcom-rpmhcc: Add RPMHCC bindings for QCS615
Add bindings and update documentation for clock rpmh driver on QCS615
SoCs.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241022-qcs615-clock-driver-v4-1-3d716ad0d987@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25 22:53:22 -06:00
Konrad Dybcio
089c09ee12 dt-bindings: clock: qcom,x1e80100-gcc: Add X1P42100
X1P42100 is based on X1E80100 and largely reuses the X1E80100's GCC
block, adding a couple wires here and there.

Add a compatible for the X1P4 with a fallback to X1E80100. There are
some additions in the smaller one, that will be added in the future.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241221-topic-x1p4_clk-v1-1-dbaeccb74884@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25 21:57:36 -06:00
Bjorn Andersson
75c5cb35a8 Merge branch '20241221-topic-x1p4_clk-v1-2-dbaeccb74884@oss.qualcomm.com' into clk-for-6.14
Merge the X1P42100 GPUCC binding through a topic branch to make
available for the DeviceTree branch as well.
2024-12-25 21:56:50 -06:00
Konrad Dybcio
e8f81b5613 dt-bindings: clock: qcom,x1e80100-gpucc: Extend for X1P42100
To make it easier for X1P4 and X1E to share a common device tree base,
extend the existing latter's GPUCC bindings and reuse them on the
former platform.

While not in the same file, it only makes sense to introduce the new
compatible in this commit as well.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241221-topic-x1p4_clk-v1-2-dbaeccb74884@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25 21:56:30 -06:00
Konrad Dybcio
5deec162b2 dt-bindings: arm: qcom: Add X1P42100 SoC & CRD
The X1 family is split into two parts: the 10- and 12-core parts are
variants of the same silicon with different fusing, whereas the 8-core
ones are a separate design. Thankfully, the software interface is only
barely different, letting us reuse much of the existing X1 work.

Add X1P42100 SoC (and the CRD based on it) as a representative of the
8-core series.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20241221-topic-x1p4_soc-v1-2-55347831d73c@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25 21:55:29 -06:00
Konrad Dybcio
13dcb0eff1 dt-bindings: arm: qcom-soc: Extend X1E prefix match for X1P
The X1 series includes SoCs like X1P42100. Extend the pattern x1e match
to x1[ep] to also include these.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20241221-topic-x1p4_soc-v1-1-55347831d73c@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-12-25 21:55:29 -06:00
Neil Armstrong
af1bc0ebe7 dt-bindings: phy: qcom,qmp-pcie: document the SM8350 two lanes PCIe PHY
Document the two lanes PCIe PHY found on SM8350 SoCs along the
already documented single lane PCIe PHY.

This fixes:
/soc@0/phy@1c0e000: failed to match any schema with compatible: ['qcom,sm8350-qmp-gen3x2-pcie-phy']

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241204-topic-misc-sm8350-pcie-bindings-fix-v1-1-e8eaff1699d7@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-25 01:17:33 +05:30
Manikanta Mylavarapu
74a5054ee9 dt-bindings: phy: qcom,ipq8074-qmp-pcie: Document the IPQ5424 QMP PCIe PHYs
Document the PCIe phy on the IPQ5424 platform using the
IPQ9574 bindings as a fallback, since the PCIe phy on the
IPQ5424 is similar to IPQ9574.

Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241213134950.234946-3-quic_mmanikan@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-25 01:17:33 +05:30
Abhinav Kumar
c36c60d1f7 dt-bindings: display: msm: dp: update maintainer entry
Add myself as maintainer for dp controller yaml as to support
review of the incoming changes.

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/626921/
Link: https://lore.kernel.org/r/20241202-dp_mst_bindings-v1-4-9a9a43b0624a@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2024-12-24 20:57:59 +02:00
Krishna Kurapati
413918c44c dt-bindings: usb: qcom,dwc3: Add QCS615 to USB DWC3 bindings
Update dt-bindings to add primary controller of QCS615 to USB
DWC3 controller list.

Although this controller has a QUSB2 Phy, it belongs to a
generation of SoCs like SDM670/SDM845/SM6350 where DP/DM is
used for wakeup instead of qusb2_phy interrupt.

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241224084621.4139021-2-krishna.kurapati@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24 20:02:50 +05:30
Niravkumar L Rabara
1f05f823a1 dt-bindings: mtd: cadence: convert cadence-nand-controller.txt to yaml
Convert cadence-nand-controller.txt to yaml format.
Update cadence-nand-controller.txt to cdns,hp-nfc.yaml in MAINTAINER file.

Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2024-12-24 13:15:31 +01:00
Hui-Ping Chen
c20e060190 dt-bindings: mtd: nuvoton,ma35d1-nand: add new bindings
Add dt-bindings for the Nuvoton MA35 SoC NAND Controller.

Signed-off-by: Hui-Ping Chen <hpchen0nvt@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
2024-12-24 13:12:59 +01:00
Charan Pedumuru
5d6670033a dt-bindings: dma: atmel: Convert to json schema
Convert old text based binding to json schema.
Changes during conversion:
- Add the required properties `clock` and `clock-names`, which were
  missing in the original binding.
- Add a fallback for `microchip,sam9x7-dma` and `microchip,sam9x60-dma`
  as they are compatible with the dma IP core on `atmel,sama5d4-dma`.
- Update examples and include appropriate file directives to resolve
  errors identified by `dt_binding_check` and `dtbs_check`.

Signed-off-by: Charan Pedumuru <charan.pedumuru@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241205-xdma-v1-1-76a4a44670b5@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24 16:07:00 +05:30
Ken Sloat
54e09c8e2d dt-bindings: dma: st-stm32-dmamux: Add description for dma-cell values
The dma-cell values for the stm32-dmamux are used to craft the DMA spec
for the actual controller. These values are currently undocumented
leaving the user to reverse engineer the driver in order to determine
their meaning. Add a basic description, while avoiding duplicating
information by pointing the user to the associated DMA docs that
describe the fields in depth.

Signed-off-by: Ken Sloat <ksloat@cornersoftsolutions.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Amelie Delaunay <amelie.delaunay@foss.st.com>
Link: https://lore.kernel.org/r/20241206115018.1155149-1-ksloat@cornersoftsolutions.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24 16:06:23 +05:30
David Lechner
06d5363296 dt-bindings: dma: adi,axi-dmac: deprecate adi,channels node
Deprecate the adi,channels node in the adi,axi-dmac binding. Prior to
IP version 4.3.a, this information was required. Since then, there are
memory-mapped registers that can be read to get the same information.

Acked-by: Nuno Sa <nuno.sa@analog.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://lore.kernel.org/r/20241216-axi-dma-dt-yaml-v3-2-7b994710c43f@baylibre.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24 15:48:08 +05:30
David Lechner
788726fcea dt-bindings: dma: adi,axi-dmac: convert to yaml schema
Convert the AXI DMAC bindings from .txt to .yaml.

Acked-by: Nuno Sa <nuno.sa@analog.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: David Lechner <dlechner@baylibre.com>
Link: https://lore.kernel.org/r/20241216-axi-dma-dt-yaml-v3-1-7b994710c43f@baylibre.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24 15:48:08 +05:30
Mohan Kumar D
762b37fc6a dt-bindings: dma: Support channel page to nvidia,tegra210-adma
Multiple ADMA Channel page hardware support has been added from
TEGRA186 and onwards. Update the DT binding to use any of the
ADMA channel page address space region.

Signed-off-by: Mohan Kumar D <mkumard@nvidia.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241217074358.340180-2-mkumard@nvidia.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24 15:34:04 +05:30
Vaishnav Achath
775363772f dt-bindings: dma: ti: k3-bcdma: Add J722S CSI BCDMA
J722S CSI BCDMA is similar to J721S2 CSI BCDMA and supports both RX and TX
channels but has a different PSIL thread base ID which is currently
handled in k3-udma driver. Add an entry for J722S CSIRX BCDMA.

Signed-off-by: Vaishnav Achath <vaishnav.a@ti.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241127101627.617537-2-vaishnav.a@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24 15:32:21 +05:30
Larisa Grigore
57eeb0a566 dt-bindings: dma: fsl-edma: add nxp,s32g2-edma compatible string
Introduce the compatible strings 'nxp,s32g2-edma' and 'nxp,s32g3-edma' to
enable the support for the eDMAv3 present on S32G2/S32G3 platforms.

The S32G2/S32G3 eDMA architecture features 32 DMA channels. Each of the
two eDMA instances is integrated with two DMAMUX blocks.

Another particularity of these SoCs is that the interrupts are shared
between channels in the following way:
- DMA Channels 0-15 share the 'tx-0-15' interrupt
- DMA Channels 16-31 share the 'tx-16-31' interrupt
- all channels share the 'err' interrupt

Signed-off-by: Larisa Grigore <larisa.grigore@oss.nxp.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241219102415.1208328-4-larisa.grigore@oss.nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
2024-12-24 15:14:13 +05:30
Amit Sunil Dhamne
1ed739929c dt-bindings: connector: Add pd-revision property
Add pd-revision property definition, to specify the maximum Power
Delivery Revision and Version supported by the connector.

Signed-off-by: Amit Sunil Dhamne <amitsd@google.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241210-get_rev_upstream-v2-1-d0094e52d48f@google.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-12-24 08:56:04 +01:00
Stephan Gerhold
d21bbeee52 dt-bindings: usb: gpio-sbu-mux: Add an entry for FSUSB42
Add a compatible entry for the onsemi FSUSB42 USB switch, which can be used
for switching orientation of the SBU lines in USB Type-C applications.

Drivers work as-is with the existing fallback compatible.

Link to datasheet: https://www.onsemi.com/pdf/datasheet/fsusb42-d.pdf

Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241212-x1e80100-qcp-dp-v1-1-37cb362a0dfe@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-12-24 08:56:04 +01:00
Daniel Machon
f0706c0472 dt-bindings: net: sparx5: document RGMII delays
The lan969x switch device supports two RGMII port interfaces that can be
configured for MAC level rx and tx delays. Document two new properties
{rx,tx}-internal-delay-ps in the bindings, used to select these delays.

Tested-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Link: https://patch.msgid.link/20241220-sparx5-lan969x-switch-driver-4-v5-9-fa8ba5dff732@microchip.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
2024-12-23 10:57:56 -08:00
Ian Rogers
518413d89c perf Documentation: Describe the PMU naming convention
It is an existing convention to use suffixes with PMU names. Try to
capture that convention so that future PMU devices may adhere to it.

The name of the file and date within the file try to follow existing
conventions, particularly sysfs-bus-event_source-devices-events.

Reviewed-by: James Clark <james.clark@arm.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Reviewed-by: Leo Yan <leo.yan@arm.com>
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Ian Rogers <irogers@google.com>
Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Bharat Bhushan <bbhushan2@marvell.com>
Cc: Bhaskara Budiredla <bbudiredla@marvell.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ravi Bangoria <ravi.bangoria@amd.com>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Richter <tmricht@linux.ibm.com>
Cc: Tuan Phan <tuanphan@os.amperecomputing.com>
Cc: Will Deacon <will@kernel.org>
Link: https://lore.kernel.org/r/20240606044959.335715-1-irogers@google.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2024-12-23 13:53:08 -03:00
Charan Pedumuru
2351998fd8 dt-bindings: net: can: atmel: Convert to json schema
Convert old text based binding to json schema.
Changes during conversion:
- Add a fallback for `microchip,sam9x60-can` as it is compatible with the
  CAN IP core on `atmel,at91sam9x5-can`.
- Add the required properties `clock` and `clock-names`, which were
  missing in the original binding.
- Update examples and include appropriate file directives to resolve
  errors identified by `dt_binding_check` and `dtbs_check`.

Signed-off-by: Charan Pedumuru <charan.pedumuru@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20241120-can-v3-1-da5bb4f6128d@microchip.com
[mkl: fixed indention in example]
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
2024-12-23 12:39:12 +01:00
Nick Chan
a248d90ddc dt-bindings: cpufreq: apple,cluster-cpufreq: Add A7-A11, T2 compatibles
Add compatibles for Apple A7-A11, T2 SoCs.

Apple A7, A8, A8X gets the per-SoC compatible and the A7
"apple,s5l8960x-cluster-cpufreq" compatible.

Apple A9, A9X, A10, A10X, T2, A11 gets the per-SoC compatible, M1
"apple,t8103-cluster-cpufreq" compatible, then the
"apple,cluster-cpufreq" fallback compatible.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nick Chan <towinchenmi@gmail.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2024-12-23 16:26:44 +05:30
Christian Marangi
ab16dfb99c dt-bindings: cpufreq: Document support for Airoha EN7581 CPUFreq
On newer Airoha SoC, CPU Frequency is scaled indirectly with SMC commands
to ATF.

A virtual clock is exposed. This virtual clock is a get-only clock and
is used to expose the current global CPU clock. The frequency info comes
by the output of the SMC command that reports the clock in MHz.

The SMC sets the CPU clock by providing an index, this is modelled as
performance states in a power domain.

CPUs can't be individually scaled as the CPU frequency is shared across
all CPUs and is global.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2024-12-23 16:26:44 +05:30
Vicentiu Galanopulo
0fffcd4e7c dt-bindings: leds: Add LED1202 LED Controller
The LED1202 is a 12-channel low quiescent current LED driver with:
  * Supply range from 2.6 V to 5 V
  * 20 mA current capability per channel
  * 1.8 V compatible I2C control interface
  * 8-bit analog dimming individual control
  * 12-bit local PWM resolution
  * 8 programmable patterns

If the led node is present in the controller then the channel is
set to active.

Signed-off-by: Vicentiu Galanopulo <vicentiu.galanopulo@remote-tech.co.uk>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241218182001.41476-3-vicentiu.galanopulo@remote-tech.co.uk
Signed-off-by: Lee Jones <lee@kernel.org>
2024-12-23 10:13:32 +00:00
Vicentiu Galanopulo
b1816b2238 Documentation:leds: Add leds-st1202.rst
Add usage for sysfs hw_pattern entry for leds-st1202

Signed-off-by: Vicentiu Galanopulo <vicentiu.galanopulo@remote-tech.co.uk>
Link: https://lore.kernel.org/r/20241218182001.41476-2-vicentiu.galanopulo@remote-tech.co.uk
Signed-off-by: Lee Jones <lee@kernel.org>
2024-12-23 10:13:32 +00:00
Greg Kroah-Hartman
d3571faa1b Merge 6.14-rc4 into usb-next
We need the USB fixes in here as well for testing.

Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2024-12-23 07:59:03 +01:00
Linus Torvalds
bcde95ce32 Merge tag 'devicetree-fixes-for-6.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree fixes from Rob Herring:

 - Disable #address-cells/#size-cells warning on coreboot (Chromebooks)
   platforms

 - Add missing root #address-cells/#size-cells in default empty DT

 - Fix uninitialized variable in of_irq_parse_one()

 - Fix interrupt-map cell length check in of_irq_parse_imap_parent()

 - Fix refcount handling in __of_get_dma_parent()

 - Fix error path in of_parse_phandle_with_args_map()

 - Fix dma-ranges handling with flags cells

 - Drop explicit fw_devlink handling of 'interrupt-parent'

 - Fix "compression" typo in fixed-partitions binding

 - Unify "fsl,liodn" property type definitions

* tag 'devicetree-fixes-for-6.13-1' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux:
  of: Add coreboot firmware to excluded default cells list
  of/irq: Fix using uninitialized variable @addr_len in API of_irq_parse_one()
  of/irq: Fix interrupt-map cell length check in of_irq_parse_imap_parent()
  of: Fix refcount leakage for OF node returned by __of_get_dma_parent()
  of: Fix error path in of_parse_phandle_with_args_map()
  dt-bindings: mtd: fixed-partitions: Fix "compression" typo
  of: Add #address-cells/#size-cells in the device-tree root empty node
  dt-bindings: Unify "fsl,liodn" type definitions
  of: address: Preserve the flags portion on 1:1 dma-ranges mapping
  of/unittest: Add empty dma-ranges address translation tests
  of: property: fw_devlink: Do not use interrupt-parent directly
2024-12-22 08:40:23 -08:00
Randy Dunlap
135ec43eb2 fiemap: use kernel-doc includes in fiemap docbook
Add some kernel-doc notation to structs in fiemap header files
then pull that into Documentation/filesystems/fiemap.rst
instead of duplicating the header file structs in fiemap.rst.
This helps to future-proof fiemap.rst against struct changes.

Add missing flags documentation from header files into fiemap.rst
for FIEMAP_FLAG_CACHE and FIEMAP_EXTENT_SHARED.

Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
Link: https://lore.kernel.org/r/20241121011352.201907-1-rdunlap@infradead.org
Cc: Christoph Hellwig <hch@lst.de>
Cc: Alexander Viro <viro@zeniv.linux.org.uk>
Cc: Christian Brauner <brauner@kernel.org>
Cc: Jan Kara <jack@suse.cz>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: linux-doc@vger.kernel.org
Cc: Matthew Wilcox <willy@infradead.org>
Signed-off-by: Christian Brauner <brauner@kernel.org>
2024-12-22 11:29:50 +01:00