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Author SHA1 Message Date
Rohit Visavalia
b00b08a596 dt-bindings: clock: xilinx: Add reset GPIO for VCU 
It is marked as optional as some of the ZynqMP designs are having vcu_reset
(reset pin of VCU IP) driven by proc_sys_reset, proc_sys_reset is another
PL IP driven by the PS pl_reset. So, here the VCU reset is not driven by
axi_gpio or PS GPIO so there will be no GPIO entry.

Signed-off-by: Rohit Visavalia <rohit.visavalia@amd.com>
Link: https://lore.kernel.org/r/20250107044038.100945-3-rohit.visavalia@amd.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-01-07 11:48:23 -08:00
Rohit Visavalia
b51adc7755 dt-bindings: clock: xilinx: Convert VCU bindings to dtschema 
Convert AMD (Xilinx) VCU bindings to yaml format.
Additional changes:
   - move xlnx_vcu DT binding to clock from soc following commit
     a2fe7baa27 ("clk: xilinx: move xlnx_vcu clock driver from soc")
   - corrected clock sequence as per xilinx device-tree generator

Signed-off-by: Rohit Visavalia <rohit.visavalia@xilinx.com>
Link: https://lore.kernel.org/r/20250107044038.100945-2-rohit.visavalia@amd.com
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-01-07 11:48:14 -08:00
Stephen Boyd
83f6c3dea9 Merge tag 'renesas-clk-for-v6.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas 
Pull Renesas clk driver updates from Geert Uytterhoeven:

  - Add support for the RZ/G3E (R9A09G047) SoC
  - Add Module Stop (MSTOP) support on RZ/V2H
  - Add Image Signal Processor helper block (FCPVX and VSPX) clocks on
    R-Car V4H SoC
  - Add System Controller (SYS) reset and Generic Interrupt Controller
    (GIC) clock and reset entries on RZ/V2H

* tag 'renesas-clk-for-v6.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guard
  clk: renesas: r9a09g057: Add clock and reset entries for GIC
  clk: renesas: r9a09g057: Add reset entry for SYS
  clk: renesas: r8a779g0: Add VSPX clocks
  clk: renesas: r8a779g0: Add FCPVX clocks
  clk: renesas: r9a09g047: Add I2C clocks/resets
  clk: renesas: r9a09g047: Add CA55 core clocks
  clk: renesas: rzv2h: Add support for RZ/G3E SoC
  clk: renesas: rzv2h: Add MSTOP support
  dt-bindings: clock: renesas: Document RZ/G3E SoC CPG
  dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK
  dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants
 2025-01-07 11:42:23 -08:00
Niravkumar L Rabara
456f3000f8 dt-bindings: soc: altera: convert socfpga-system.txt to yaml 
Convert socfpga-system.txt to altr,socfpga-sys-mgr.yaml and move to
soc directory.

Add platform names in description for clarity. ARM(32-bit) platforms
Cyclone5, Arria5 and Arria10 is using "altr,sys-mgr" compatible,
while ARM64 is using "altr,sys-mgr-s10" compatible.
Removed "cpu1-start-addr" for ARM64 as it is not required.

Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Link: https://lore.kernel.org/r/20250107105129.2784203-1-niravkumar.l.rabara@intel.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-01-07 12:58:36 -06:00
Mark Brown
c51187903f ASoC: codecs: Add aw88083 amplifier driver 
Merge series from wangweidong.a@awinic.com:

Add the awinic,aw88083 property to support the aw88083 chip.

The driver is for amplifiers aw88083 of Awinic Technology
Corporation. The AW88083 is an intelligent digital audio
amplifier with low noise.
 2025-01-07 18:50:45 +00:00
John Erasmus Mari Geronimo
adc52dd407 hwmon: (pmbus/adm1275) add adm1273 support 
Add support for adm1273 which is similar to adm1275 and other chips
of the series.

Signed-off-by: John Erasmus Mari Geronimo <johnerasmusmari.geronimo@analog.com>
Link: https://lore.kernel.org/r/20250106131740.305988-3-johnerasmusmari.geronimo@analog.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
 2025-01-07 09:08:10 -08:00
John Erasmus Mari Geronimo
2b2b62a911 dt-bindings: hwmon: adm1275: add adm1273 
Add support for the adm1273 Hot-Swap Controller and Digital Power
and Energy Monitor

Signed-off-by: John Erasmus Mari Geronimo <johnerasmusmari.geronimo@analog.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250106131740.305988-2-johnerasmusmari.geronimo@analog.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
 2025-01-07 09:07:35 -08:00
Christoph Schlameuss
5021fd77d6 KVM: s390: Reject KVM_SET_GSI_ROUTING on ucontrol VMs 
Prevent null pointer dereference when processing
KVM_IRQ_ROUTING_S390_ADAPTER routing entries.
The ioctl cannot be processed for ucontrol VMs.

Fixes: f65470661f ("KVM: s390/interrupt: do not pin adapter interrupt pages")
Signed-off-by: Christoph Schlameuss <schlameuss@linux.ibm.com>
Tested-by: Hariharan Mari <hari55@linux.ibm.com>
Reviewed-by: Hariharan Mari <hari55@linux.ibm.com>
Reviewed-by: Claudio Imbrenda <imbrenda@linux.ibm.com>
Link: https://lore.kernel.org/r/20241216092140.329196-4-schlameuss@linux.ibm.com
Message-ID: <20241216092140.329196-4-schlameuss@linux.ibm.com>
Signed-off-by: Claudio Imbrenda <imbrenda@linux.ibm.com>
 2025-01-07 16:36:11 +01:00
Christoph Schlameuss
df989238fa KVM: s390: Reject setting flic pfault attributes on ucontrol VMs 
Prevent null pointer dereference when processing the
KVM_DEV_FLIC_APF_ENABLE and KVM_DEV_FLIC_APF_DISABLE_WAIT ioctls in the
interrupt controller.

Fixes: 3c038e6be0 ("KVM: async_pf: Async page fault support on s390")
Reported-by: Claudio Imbrenda <imbrenda@linux.ibm.com>
Signed-off-by: Christoph Schlameuss <schlameuss@linux.ibm.com>
Reviewed-by: Hariharan Mari <hari55@linux.ibm.com>
Reviewed-by: Claudio Imbrenda <imbrenda@linux.ibm.com>
Link: https://lore.kernel.org/r/20241216092140.329196-2-schlameuss@linux.ibm.com
Message-ID: <20241216092140.329196-2-schlameuss@linux.ibm.com>
Signed-off-by: Claudio Imbrenda <imbrenda@linux.ibm.com>
 2025-01-07 16:36:10 +01:00
Melody Olvera
6143cc1d9e dt-bindings: interrupt-controller: qcom,pdc: Document SM8750 PDC 
Document the PDC block on the SM8750 SoC.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Link: https://lore.kernel.org/r/20241204-sm8750_master_pdc-v1-1-3a06cb62a28f@quicinc.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-01-07 09:10:11 -06:00
Rob Herring (Arm)
92c58adcee dt-bindings: memory-controller: qca,ath79-ddr-controller: Drop consumer from example 
Normal practice is examples only show what the binding document defines
and doesn't include consumers in a provider example (or vice-versa). The
"qca,ddr-wb-channel-interrupts" and "qca,ddr-wb-channels" properties are
also not yet documented by a schema, so avoid (not yet enabled) warnings
on them by dropping the interrupt-controller node from the example.

Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20250103212448.2852884-1-robh@kernel.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-01-07 08:35:34 -06:00
AngeloGioacchino Del Regno
157660a581 dt-bindings: sram: qcom,imem: Document MSM8976 
Add compatible for MSM8976 IMEM.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221111120156.48040-5-angelogioacchino.delregno@collabora.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-01-07 08:35:34 -06:00
Rayyan Ansari
fed79caaf7 dt-bindings: thermal: qcom-tsens: Document ipq6018 temperature sensor 
Document the ipq6018 temperature sensor, which is used in ipq6018.dtsi
and is compatible with the ipq8074 temperature sensor.

Signed-off-by: Rayyan Ansari <rayyan.ansari@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240716133803.82907-1-rayyan.ansari@linaro.org
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-01-07 08:35:34 -06:00
Jingyi Wang
715e36194d dt-bindings: qcom,pdc: document QCS8300 Power Domain Controller 
Document Power Domain Controller for Qualcomm QCS8300. PDC is included
in QCS8300 SoC. This controller acts as an interrupt controller, enabling
the detection of interrupts when the GIC is non-operational.

Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20240911-qcs8300_binding-v2-1-de8641b3eaa1@quicinc.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-01-07 08:35:34 -06:00
Lijuan Gao
9a3c545b61 dt-bindings: qcom,pdc: document QCS615 Power Domain Controller 
Add a compatible for the Power Domain Controller on QCS615 platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
Link: https://lore.kernel.org/r/20241104-add_initial_support_for_qcs615-v5-2-9dde8d7b80b0@quicinc.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-01-07 08:35:34 -06:00
Krzysztof Kozlowski
fffe003fc2 ASoC: dt-bindings: Correct indentation and style in DTS example 
DTS example in the bindings should be indented with 2- or 4-spaces and
aligned with opening '- |', so correct any differences like 3-spaces or
mixtures 2- and 4-spaces in one binding.  While touching the lines do
other non-functional changes: replace raw number with proper define for
GPIO flag and use generic node name.

No functional changes here, but saves some comments during reviews of
new patches built on existing code.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://patch.msgid.link/20250107125901.227995-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
 2025-01-07 14:28:08 +00:00
Bibek Kumar Patro
ef4144b1b4 iommu/arm-smmu: Re-enable context caching in smmu reset operation 
Default MMU-500 reset operation disables context caching in prefetch
buffer. It is however expected for context banks using the ACTLR
register to retain their prefetch value during reset and runtime
suspend.

Add config 'ARM_SMMU_MMU_500_CPRE_ERRATA' to gate this errata workaround
in default MMU-500 reset operation which defaults to 'Y' and provide
option to disable workaround for context caching in prefetch buffer as
and when needed.

Suggested-by: Will Deacon <will@kernel.org>
Signed-off-by: Bibek Kumar Patro <quic_bibekkum@quicinc.com>
Link: https://lore.kernel.org/r/20241212151402.159102-2-quic_bibekkum@quicinc.com
Signed-off-by: Will Deacon <will@kernel.org>
 2025-01-07 13:26:28 +00:00
Jianbo Liu
373b79af3a xfrm: Support ESN context update to hardware for TX 
Previously xfrm_dev_state_advance_esn() was added for RX only. But
it's possible that ESN context also need to be synced to hardware for
TX, so call it for outbound in this patch.

Signed-off-by: Jianbo Liu <jianbol@nvidia.com>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
Signed-off-by: Steffen Klassert <steffen.klassert@secunet.com>
 2025-01-07 13:12:11 +01:00
Val Packett
3b19239ad4 dt-bindings: mediatek,mt6779-keypad: add more compatibles 
Add compatibles for SoCs using this device (mt8183, mt8365, mt8516).

Signed-off-by: Val Packett <val@packett.cool>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20241225192631.25017-2-val@packett.cool
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
 2025-01-07 13:11:54 +01:00
Hsiao Chien Sung
5086c55a95 dt-bindings: display: mediatek: ovl: Modify rules for MT8195/MT8188 
Modify rules for both MT8195 and MT8188.
Hardware capabilities include color formats and AFBC are
changed since MT8195, stop using the settings of MT8183.

Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Link: https://lore.kernel.org/r/20241219181531.4282-3-jason-jh.lin@mediatek.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
 2025-01-07 13:11:49 +01:00
Jason-JH.Lin
4726336c6b dt-bindings: display: mediatek: ovl: Add compatible strings for MT8188 MDP3 
Add compatible strings for the MDP3 OVL hardware components in
MediaTek's MT8188 SoC and it is compatible with the existing
MT8195 MDP OVL components.

Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Suggested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241219181531.4282-2-jason-jh.lin@mediatek.com
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
 2025-01-07 13:11:49 +01:00
Chen-Yu Tsai
5c9f4bc4b6 dt-bindings: arm: mediatek: Drop MT8192 Chromebook variants that never shipped 
The Hayato rev5 sku2 and Spherion rev4 variants were designed in
anticipation of shortages of the headphone codec. This never happened.
As far as our records show: the variants were never produced or
shipped, and no such devices were deployed to any lab.

Drop them.

Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241224084839.2904335-1-wenst@chromium.org
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
 2025-01-07 13:11:48 +01:00
Krzysztof Kozlowski
c5aa327e10 media: dt-bindings: trivial white-space and example cleanup 
Minor cleanups without funcitonal impact:
 - There should not be an empty blank line after SPDX tag,
 - Convention is to indent DTS examples in coding style with 2- or
   4-space indentation (4 is preferred),
 - Drop unused labels in DTS examples.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans Verkuil <hverkuil@xs4all.nl>
 2025-01-07 12:21:44 +01:00
John Audia
a045a189f4 hwmon: (nct6683) Add another customer ID for MSI 
The new customer ID was found on a MPG X870E CARBON WIFI (MS-7E49) with
a NCT6687D chip.

Signed-off-by: John Audia <therealgraysky@proton.me>
[groeck: Resolved conflicts in Documentation/hwmon/nct6683.rst]
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
 2025-01-06 19:21:31 -08:00
Richard Acayan
bf6aa2d693 dt-bindings: clock: qcom,sdm845-camcc: add sdm670 compatible 
The camera clocks on SDM670 and SDM845 have no significant differences
that would require a change in the clock controller driver. The only
difference is the clock frequency at each level of the power domains,
which is not specified in the clock driver. There should still be a
compatible specific to the SoC, so add the compatible for SDM670 with
the SDM845 compatible as fallback.

Link: d4dc50c0a9/drivers/clk/qcom/camcc-sdm845.c (2048)
Suggested-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Suggested-by: Konrad Dybcio <konradybcio@kernel.org>
Link: https://lore.kernel.org/linux-arm-msm/7d26a62b-b898-4737-bd53-f49821e3b471@linaro.org
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241218231729.270137-8-mailingradian@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-01-06 18:10:53 -06:00
Dmitry Baryshkov
2b5add606c dt-bindings: clock: qcom,mmcc: support LVDS PLL input for apq8064 
APQ8064 / MSM8960 have separate LVDS PLL driving the LVDS / LCDC clock.
Add corresponding input to clock controller bindings.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241224-apq8064-fix-mmcc-v1-1-c95d2e2bf143@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-01-06 18:05:27 -06:00
Dario Binacchi
caa508a38e dt-bindings: clock: st,stm32mp1-rcc: complete the reference path 
All other paths referenced in the file follow a scheme starting from the
Linux root. The patch adjusts the single file that deviated from this
scheme, making it consistent with the others.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/r/20241231150144.4035938-2-dario.binacchi@amarulasolutions.com
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-01-06 15:48:05 -08:00
Dario Binacchi
c5dcc2804d dt-bindings: clock: st,stm32mp1-rcc: fix reference paths 
The path of the two files was wrong even at the time they were added.
Let's fix them so they can be correctly referenced.

Fixes: 722dc8a1d5 ("dt-bindings: rcc: stm32: add new compatible for STM32MP13 SoC")
Fixes: 20107d7328 ("dt-bindings: rcc: Convert stm32mp1 rcc bindings to json-schema")
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Link: https://lore.kernel.org/r/20241231150144.4035938-1-dario.binacchi@amarulasolutions.com
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-01-06 15:48:01 -08:00
Andreas Kemnade
dc39d7fa60 dt-bindings: clock: ti: Convert composite.txt to json-schema 
Convert the OMAP gate clock device tree binding to json-schema.
Specify the creator of the original binding as a maintainer.
Choose GPL-only license because original binding was also GPL.

Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Link: https://lore.kernel.org/r/20250105170854.408875-3-andreas@kemnade.info
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-01-06 15:45:34 -08:00
Andreas Kemnade
be7638a0d5 dt-bindings: clock: ti: Convert gate.txt to json-schema 
Convert the OMAP gate clock device tree binding to json-schema.
Specify the creator of the original binding as a maintainer.
Choose GPL-only license because original binding was also GPL.
Clean up the examples during conversion to meet modern standards and
remove examples with no additional value.
Due to usage in code and existing devicetree binding, add the
ti,set-rate-parent property.

Signed-off-by: Andreas Kemnade <andreas@kemnade.info>
Link: https://lore.kernel.org/r/20250105170854.408875-2-andreas@kemnade.info
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2025-01-06 15:45:11 -08:00
Bjorn Andersson
a53c9b278a Merge branch '20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com' into arm64-for-6.14 
Merge the IPQ CMN PLL clock binding from its topic branch to gain access
to the clock constants.
 2025-01-06 17:42:27 -06:00
Bjorn Andersson
62ede76a7b Merge branch '20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com' into clk-for-6.14 
Merge the IPQ CMN PLL clock binding through a topic branch to make it
available to DeviceTree source branches as well.
 2025-01-06 17:41:49 -06:00
Luo Jie
c0f1cbf795 dt-bindings: clock: qcom: Add CMN PLL clock controller for IPQ SoC 
The CMN PLL controller provides clocks to networking hardware blocks
and to GCC on Qualcomm IPQ9574 SoC. It receives input clock from the
on-chip Wi-Fi, and produces output clocks at fixed rates. These output
rates are predetermined, and are unrelated to the input clock rate.
The primary purpose of CMN PLL is to supply clocks to the networking
hardware such as PPE (packet process engine), PCS and the externally
connected switch or PHY device. The CMN PLL block also outputs fixed
rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep
clock supplied to GCC.

Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-01-06 17:41:39 -06:00
Luca Weiss
36036a164f dt-bindings: eeprom: at24: Add compatible for Puya P24C256C 
Add the compatible for an 256Kb EEPROM from Puya.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250103-fp5-cam-eeprom-v1-3-88dee1b36f8e@fairphone.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
 2025-01-06 21:20:31 +01:00
Luca Weiss
eace9d83c8 dt-bindings: vendor-prefixes: Add Puya Semiconductor (Shanghai) Co., Ltd. 
Add the vendor prefix for a manufacturer of EEPROM chips among others.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250103-fp5-cam-eeprom-v1-2-88dee1b36f8e@fairphone.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
 2025-01-06 21:20:30 +01:00
Luca Weiss
56d4ef115c dt-bindings: eeprom: at24: Add compatible for Giantec GT24P128F 
Add the compatible for another 128Kb EEPROM from Giantec.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250103-fp5-cam-eeprom-v1-1-88dee1b36f8e@fairphone.com
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
 2025-01-06 21:20:30 +01:00
Kyle Deng
89ec0f57a7 dt-bindings: mailbox: qcom,apcs-kpss-global: Document the qcs615 APSS 
Add compatible for the Qualcomm qcs615 mailbox block.
QCS615 mailbox is compatible with SDM845 use fallback for it.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Kyle Deng <quic_chunkaid@quicinc.com>
Link: https://lore.kernel.org/r/20241018073417.2338864-2-quic_chunkaid@quicinc.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-01-06 13:22:37 -06:00
Lijuan Gao
38a498a281 dt-bindings: nvmem: qfprom: Add compatible for QCS615 
Document compatible for QFPROM used on QCS615. It's compatible
with generic QFPROM fallback.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
Link: https://lore.kernel.org/all/20240912-add_qfprom_compatible_for_qcs615-v1-1-9ef2e26c14ee@quicinc.com/
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-01-06 13:13:57 -06:00
Andrea Righi
e4975ac535 sched_ext: update scx_bpf_dsq_insert() doc for SCX_DSQ_LOCAL_ON 
With commit 5b26f7b920 ("sched_ext: Allow SCX_DSQ_LOCAL_ON for direct
dispatches"), scx_bpf_dsq_insert() can use SCX_DSQ_LOCAL_ON for direct
dispatch from ops.enqueue() to target the local DSQ of any CPU.

Update the documentation accordingly.

Fixes: 5b26f7b920 ("sched_ext: Allow SCX_DSQ_LOCAL_ON for direct dispatches")
Signed-off-by: Andrea Righi <arighi@nvidia.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
 2025-01-06 08:56:00 -10:00
Jingyi Wang
539808eef7 dt-bindings: remoteproc: qcom,sa8775p-pas: Document QCS8300 remoteproc 
Document the components used to boot the ADSP, CDSP and GPDSP on the
Qualcomm QCS8300 SoC. Use fallback to indicate the compatibility of the
remoteproc on the QCS8300 with that on the SA8775P.

Co-developed-by: Xin Liu <quic_liuxin@quicinc.com>
Signed-off-by: Xin Liu <quic_liuxin@quicinc.com>
Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240925-qcs8300_remoteproc_binding-v3-1-21b0c52b142b@quicinc.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
 2025-01-06 12:54:12 -06:00
Manikanta Mylavarapu
b3db0b5356 dt-bindings: watchdog: Document Qualcomm IPQ5424 
Add devicetree binding for watchdog present on Qualcomm IPQ5424 SoC.

Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20241120055248.657813-2-quic_mmanikan@quicinc.com
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
 2025-01-06 19:38:08 +01:00
Melody Olvera
5202bca52a dt-bindings: arm: qcom: Document SM8750 SoC and boards 
Document the SM8750 SoC binding and the boards which use it.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241204-sm8750_master_dt-v3-1-4d5a8269950b@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-01-06 10:42:54 -06:00
Bjorn Andersson
c298af2a6d Merge branch 'icc-sm8750' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc into arm64-for-6.14 
Merge SM8750 interconnect binding from topic branch, to gain access to
interconnect constants.
 2025-01-06 10:41:37 -06:00
Bjorn Andersson
05d5d3840b Merge branches '20241204-sm8750_master_clks-v3-0-1a8f31a53a86@quicinc.com' and '20250106-sm8750-dispcc-v2-1-6f42beda6317@linaro.org' into arm64-for-6.14 
Merge SM8750 gcc, tcsr and display clock bindings from topic branches,
to gain access to clock constants.
 2025-01-06 10:36:43 -06:00
Bjorn Andersson
9d46289f18 Merge branch '20250106-sm8750-dispcc-v2-1-6f42beda6317@linaro.org' into clk-for-6.14 
Merge SM8750 display clock controller bindings through topic branch, to
make available to DeviceTree source branch as well.
 2025-01-06 10:30:24 -06:00
Krzysztof Kozlowski
4f1a62e2b3 dt-bindings: clock: qcom,sm8550-dispcc: Add SM8750 DISPCC 
Add bindings for the Qualcomm SM8750 Display Clock Controller (DISPCC).
Bindings are similar to existing SM8550 and SM8650 (same clock inputs),
but the clock hierarchy is quite different and these are not compatible
devices.

The binding header was copied from downstream sources, so I retained
original copyrights.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250106-sm8750-dispcc-v2-1-6f42beda6317@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-01-06 10:30:00 -06:00
Taniya Das
6badb455ae dt-bindings: clock: qcom-rpmhcc: Add RPMHCC for SM8750 
Update the documentation for clock rpmh driver on SM8750 SoCs.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-1-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-01-06 10:28:32 -06:00
Bjorn Andersson
4188e51685 Merge branch '20241204-sm8750_master_clks-v3-0-1a8f31a53a86@quicinc.com' into clk-for-6.14 
Merge the SM8750 GCC and TCSR clock bindings through topic branch, to
allow merging into DeviceTree source branch as well.
 2025-01-06 10:27:11 -06:00
Taniya Das
8817c21a45 dt-bindings: clock: qcom: Document the SM8750 TCSR Clock Controller 
Add bindings documentation for the SM8750 Clock Controller.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-7-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-01-06 10:27:00 -06:00
Taniya Das
42b00f4456 dt-bindings: clock: qcom: Add SM8750 GCC 
Add device tree bindings for the global clock controller on Qualcomm
SM8750 platform.

Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-5-1a8f31a53a86@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2025-01-06 10:27:00 -06:00