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Author SHA1 Message Date
Yang Yingliang
a7bea084fb clk: qcom: gcc-ipq5018: change some variable static 
lpass_axim_clk_src and lpass_sway_clk_src are only
used in gcc-ipq5018.c now, change them to static.

Fixes: e3fdbef1ba ("clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018")
Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230816080113.1222352-1-yangyingliang@huawei.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-17 20:07:54 -07:00
Robert Marko
9bc66f9739 clk: qcom: gcc-ipq4019: add missing networking resets 
IPQ4019 has more networking related resets that will be required for future
wired networking support, so lets add them.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Link: https://lore.kernel.org/r/20230814104119.96858-2-robert.marko@sartura.hr
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-15 09:31:10 -07:00
Robert Marko
268edfe96a dt-bindings: clock: qcom: ipq4019: add missing networking resets 
Add bindings for the missing networking resets found in IPQ4019 GCC.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230814104119.96858-1-robert.marko@sartura.hr
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-15 09:31:10 -07:00
Otto Pflüger
d863492886 clk: qcom: gcc-msm8917: Enable GPLL0_SLEEP_CLK_SRC 
This is the parent clock of gpll0_early, so it needs to be enabled
for gpll0_early to return the correct rate. Enable GPLL0_SLEEP_CLK_SRC
by adding its existing definition to the clock list.

This clock also doesn't work with clk_alpha_pll_ops, use
clk_branch_simple_ops instead to make it enable and disable correctly.

Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de>
Link: https://lore.kernel.org/r/20230802170317.205112-3-otto.pflueger@abscue.de
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:20:11 -07:00
Otto Pflüger
593576a369 dt-bindings: clock: gcc-msm8917: Add definition for GPLL0_SLEEP_CLK_SRC 
Add the missing #define for GPLL0_SLEEP_CLK_SRC, the parent clock of
GPLL0_EARLY.

Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230802170317.205112-2-otto.pflueger@abscue.de
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:20:10 -07:00
Imran Shaik
1c16a7b794 clk: qcom: gcc-qdu1000: Update the RCGs ops 
The clock RCGs are required to be parked at safe clock source(XO)
during disable as per the hardware expectation and clk_rcg2_shared_ops
are the closest implementation for the same. Hence update the clock
RCG ops to clk_rcg2_shared_ops.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-9-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:13:18 -07:00
Imran Shaik
baa3165800 clk: qcom: gcc-qdu1000: Update the SDCC clock RCG ops 
Update the GCC SDCC clock RCG ops to clk_rcg2_floor_ops to avoid
the overclocking issues on QDU1000 and QRU1000 SoCs.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-8-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:13:18 -07:00
Imran Shaik
76346cf708 clk: qcom: gcc-qdu1000: Add support for GDSCs 
Add the GDSCs support for QDU1000 and QRU1000 SoCs.

Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-7-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:13:18 -07:00
Imran Shaik
089aad8c76 clk: qcom: gcc-qdu1000: Add gcc_ddrss_ecpri_gsi_clk support 
Add the gcc_ddrss_ecpri_gsi_clk support as per the latest hardware
version of QDU1000 and QRU100 SoCs.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-6-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:13:17 -07:00
Imran Shaik
06d71fa10f clk: qcom: gcc-qdu1000: Register gcc_gpll1_out_even clock 
gcc_gpll1_out_even clock is referenced as a parent, but not registered
with the clock framework. Hence add support to register the same.

Fixes: 1c9efb0bc0 ("clk: qcom: Add QDU1000 and QRU1000 GCC support")
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-5-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:13:17 -07:00
Imran Shaik
2524dae5cd clk: qcom: gcc-qdu1000: Fix clkref clocks handling 
Update the GCC clkref clock's halt_check to BRANCH_HALT, as it's
status bit is not inverted in the latest hardware version of QDU1000
and QRU1000 SoCs. While at it, fix the gcc clkref clock ops as well.

Fixes: 1c9efb0bc0 ("clk: qcom: Add QDU1000 and QRU1000 GCC support")
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-4-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:13:17 -07:00
Imran Shaik
b311f5d3c4 clk: qcom: gcc-qdu1000: Fix gcc_pcie_0_pipe_clk_src clock handling 
Fix the gcc pcie pipe clock handling as per the clk_regmap_phy_mux_ops
implementation to let the clock framework automatically park the clock
at XO when the clock is switched off and restore the parent when the
clock is switched on.

Fixes: 1c9efb0bc0 ("clk: qcom: Add QDU1000 and QRU1000 GCC support")
Co-developed-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-3-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:13:17 -07:00
Imran Shaik
df873243b2 dt-bindings: clock: Update GCC clocks for QDU1000 and QRU1000 SoCs 
Add support for GCC_GPLL1_OUT_EVEN and GCC_DDRSS_ECPRI_GSI_CLK clock
bindings for QDU1000 and QRU1000 SoCs. While at it, update the
maintainers list.

Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230803105741.2292309-2-quic_imrashai@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:13:17 -07:00
Konrad Dybcio
a27ac3806b clk: qcom: gcc-sm8450: Use floor ops for SDCC RCGs 
Use the floor ops to prevent warnings like this at suspend exit and boot:

mmc0: Card appears overclocked; req 800000 Hz, actual 25000000 Hz

Fixes: db0c944ee9 ("clk: qcom: Add clock driver for SM8450")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20230811-topic-8450_clk-v1-1-88031478d548@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:00:59 -07:00
Kathiravan T
90d5c043dd clk: qcom: ipq5332: drop the gcc_apss_axi_clk_src clock 
With the removal of the mem noc clocks in the commit e224dc703521 ("clk:
qcom: gcc-ipq5332: drop the mem noc clocks"), we can drop the
gcc_apss_axi_clk_src clock as well, since there are no clocks uses this
clock as a parent.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Link: https://lore.kernel.org/r/20230710102807.1189942-3-quic_kathirav@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 19:56:50 -07:00
Kathiravan T
1784d031ef clk: qcom: ipq5332: drop the mem noc clocks 
Due to the recent design changes, all the mem noc clocks will be
configured by the bootloaders and it will be access protected by the TZ
firmware. So drop these clocks from the GCC driver.

Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
Link: https://lore.kernel.org/r/20230710102807.1189942-2-quic_kathirav@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 19:56:50 -07:00
Konrad Dybcio
a6f1e86238 clk: qcom: gcc-msm8998: Don't check halt bit on some branch clks 
Some branch clocks are governed externally and we're only supposed to
send a request concerning their shutdown, not actually ensure it happens.

Use the BRANCH_HALT_SKIP define to skip checking the halt bit.

Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-6-6222fbc2916b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 19:51:04 -07:00
Konrad Dybcio
03f1b83d89 clk: qcom: gpucc-msm8998: Use the correct GPLL0 leg with old DTs 
GPUCC has its own GPLL0 legs - one for 1-1 and one for div-2 output.
Add .name lookup to make sure older DTs consume the correct clock.

Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Tested-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-5-6222fbc2916b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 19:51:04 -07:00
Konrad Dybcio
932d8c5688 clk: qcom: mmcc-msm8998: Properly consume GPLL0 inputs 
Up until now, the GPLL0_DIV MMSS input has been modeled as a fixed
child of MMSS_GPLL0_DIV that's always-on. Properly representing the
former in the GCC driver makes us unable to keep doing so.

Consume MSS_GPLL0_DIV through fw_name ("gpll0_div") as well as add a
fixed .name link to keep backwards compatibility.

Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Tested-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-4-6222fbc2916b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 19:51:03 -07:00
Konrad Dybcio
9c76c5cf4b clk: qcom: gcc-msm8998: Control MMSS and GPUSS GPLL0 outputs properly 
Up until now, we've been relying on some non-descript hardware magic
to pinkypromise turn the clocks on for us. While new SoCs shine with
that feature, MSM8998 can not always be fully trusted.

Register the MMSS and GPUSS GPLL0 legs with the CCF to allow for manual
enable voting.

Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Tested-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-3-6222fbc2916b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 19:51:03 -07:00
Konrad Dybcio
9127b3770e dt-bindings: clock: qcom,mmcc: Add GPLL0_DIV for MSM8998 
We've not been consuming that clock for no apparent reason. Describe it.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-2-6222fbc2916b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 19:51:03 -07:00
Bjorn Andersson
9d1f3f343b Merge branch '20230622-topic-8998clk-v2-1-6222fbc2916b@linaro.org' into clk-for-6.6 
Merge additional MSM8998 GCC DeviceTree binding constants through a
topic branch to make them available to the DeviceTree source tree as
well.
 2023-08-13 19:49:57 -07:00
Konrad Dybcio
238e192bed dt-bindings: clk: qcom,gcc-msm8998: Add missing GPU/MMSS GPLL0 legs 
GPLL0 has two separate outputs to both GPUSS and MMSS: one that's
2-divided and one that runs at the same rate as the GPLL0 itself.

Add the missing ones to the binding.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-1-6222fbc2916b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 19:49:47 -07:00
Sricharan Ramabadhran
e3fdbef1ba clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018 
Add support for the global clock controller found on IPQ5018
based devices.

Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Co-developed-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/r/1690533192-22220-3-git-send-email-quic_srichara@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-11 10:50:38 -07:00
Bjorn Andersson
2f6be35d7c Merge branch '1690533192-22220-2-git-send-email-quic_srichara@quicinc.com' into clk-for-6.6 
Merge the IPQ5018 GCC Devicetree binding through a topic branch, in
order to the the clock defines.
 2023-08-11 10:50:07 -07:00
Sricharan Ramabadhran
f62d184ef7 dt-bindings: clock: Add IPQ5018 clock and reset 
This patch adds support for the global clock controller found on
the IPQ5018 based devices.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/r/1690533192-22220-2-git-send-email-quic_srichara@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-11 10:46:59 -07:00
Luca Weiss
df04d166d1 clk: qcom: gcc-sm6350: Fix gcc_sdcc2_apps_clk_src 
GPLL7 is not on by default, which causes a "gcc_sdcc2_apps_clk_src: rcg
didn't update its configuration" error when booting. Set .flags =
CLK_OPS_PARENT_ENABLE to fix the error.

Fixes: 131abae905 ("clk: qcom: Add SM6350 GCC driver")
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230804-sm6350-sdcc2-v1-1-3d946927d37d@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-04 08:54:29 -07:00
Konrad Dybcio
181b66ee7c clk: qcom: reset: Use the correct type of sleep/delay based on length 
Use the fsleep() helper that (based on the length of the delay, see: [1])
chooses the correct sleep/delay functions.

[1] https://www.kernel.org/doc/Documentation/timers/timers-howto.txt

Fixes: 2cb8a39b67 ("clk: qcom: reset: Allow specifying custom reset delay")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230726-topic-qcom_reset-v3-1-5958facd5db2@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-03 20:52:32 -07:00
Arnd Bergmann
b6bcd1c0c2 clk: qcom: fix some Kconfig corner cases 
The SM_GCC_8550 symbol and others can only be built for ARM64 or when
compile testing, but it gets selected by other drivers that can also be
built for 32-bit ARCH_QCOM when not compile testing, which results in
a Kconfig warning:

WARNING: unmet direct dependencies detected for SM_GCC_8550
  Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=m] && (ARM64 || COMPILE_TEST [=n])
  Selected by [m]:
  - SM_GPUCC_8550 [=m] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=m]
  - SM_VIDEOCC_8550 [=m] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=m]

Add further 'depends on' statements to tighten this in a way that
avoids the missing dependencies.

Fixes: fd0b5b106f ("clk: qcom: Introduce SM8350 VIDEOCC")
Fixes: 441fe711be ("clk: qcom: videocc-sm8450: Add video clock controller driver for SM8450")
Fixes: f53153a379 ("clk: qcom: videocc-sm8550: Add video clock controller driver for SM8550")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230801105718.3658612-1-arnd@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-03 08:05:15 -07:00
Patrick Whewell
783cb69382 clk: qcom: gcc-sm8250: Fix gcc_sdcc2_apps_clk_src 
GPLL9 is not on by default, which causes a "gcc_sdcc2_apps_clk_src: rcg
didn't update its configuration" error when booting. Set .flags =
CLK_OPS_PARENT_ENABLE to fix the error.

Fixes: 3e5770921a ("clk: qcom: gcc: Add global clock controller driver for SM8250")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Patrick Whewell <patrick.whewell@sightlineapplications.com>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20230802210359.408-1-patrick.whewell@sightlineapplications.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-03 08:01:45 -07:00
Yang Yingliang
e39d0fa730 clk: qcom: lcc-msm8960: change pxo_parent_data to static 
The pxo_parent_data inroduced in commit bac4675a4d ("clk: qcom:
drop lcc-mdm9615 in favour of lcc-msm8960") is only used in lcc-msm8960.c
now, change it to static.

Signed-off-by: Yang Yingliang <yangyingliang@huawei.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803082125.521849-1-yangyingliang@huawei.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-03 08:01:21 -07:00
David Wronek
fd0b5ba87a clk: qcom: gcc-sc7180: Fix up gcc_sdcc2_apps_clk_src 
Set .flags = CLK_OPS_PARENT_ENABLE to fix "gcc_sdcc2_apps_clk_src: rcg
didn't update its configuration" error.

Fixes: 17269568f7 ("clk: qcom: Add Global Clock controller (GCC) driver for SC7180")
Signed-off-by: David Wronek <davidwronek@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230723190725.1619193-2-davidwronek@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-31 16:28:59 -07:00
Yassine Oudjana
bc48641a68 clk: qcom: cbf-msm8996: Add support for MSM8996 Pro 
The CBF PLL on MSM8996 Pro has a /4 post divisor instead of /2. Handle the
difference accordingly.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230527093934.101335-4-y.oudjana@protonmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-31 14:29:05 -07:00
Yassine Oudjana
434cb57732 dt-bindings: clock: qcom,msm8996-cbf: Add compatible for MSM8996 Pro 
The CBF clock on MSM8996 Pro has a different divisor compared to MSM8996
and is therefore not fully compatible with it. Add a new compatible string
to differentiate between them.

Signed-off-by: Yassine Oudjana <y.oudjana@protonmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230527093934.101335-2-y.oudjana@protonmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-31 14:29:05 -07:00
Dmitry Baryshkov
a47fa46187 clk: qcom: gcc-mdm9615: drop the cxo clock 
The gcc and lcc devices have been switched to the DT-defined cxo_board
clock. Now we can drop the manually defined cxo clock.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230512211727.3445575-9-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-31 14:25:17 -07:00
Dmitry Baryshkov
c01c9ed3ab clk: qcom: gcc-mdm9615: use parent_hws/_data instead of parent_names 
Convert the clock driver to specify parent data rather than parent
names, to actually bind using 'clock-names' specified in the DTS rather
than global clock names. Use parent_hws where possible to refer parent
clocks directly, skipping the lookup.

Note, the system names for xo clocks were changed from "cxo" to
"cxo_board" to follow the example of other platforms. This switches the
clocks to use DT-provided "cxo_board" clock instead of manually
registered "cxo" clock and allows us to drop the cxo clock.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230512211727.3445575-8-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-31 14:25:17 -07:00
Dmitry Baryshkov
1583694bb4 clk: qcom: gcc-mdm9615: use proper parent for pll0_vote clock 
The pll0_vote clock definitely should have pll0 as a parent (instead of
pll8).

Fixes: 7792a8d671 ("clk: mdm9615: Add support for MDM9615 Clock Controllers")
Cc: stable@kernel.org
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230512211727.3445575-7-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-31 14:25:17 -07:00
Dmitry Baryshkov
bac4675a4d clk: qcom: drop lcc-mdm9615 in favour of lcc-msm8960 
The two LCC drivers, msm8960 and mdm9615 are almost the same. The only
difference is the platform clock: msm8960/apq8064 use pxo, while mdm9615
uses cxo. Drop the lcc-mdm9615 in favour of using lcc-msm8960 instead.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230512211727.3445575-6-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-31 14:25:16 -07:00
Dmitry Baryshkov
6bab5dab6e clk: qcom: gcc-mdm9615: use ARRAY_SIZE instead of specifying num_parents 
Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
adding/removing entries to/from parent_data easy and errorproof.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230512211727.3445575-5-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-31 14:24:04 -07:00
Dmitry Baryshkov
b7fd5d19e3 dt-bindings: clock: provide separate bindings for qcom,gcc-mdm9615 
The global clock controller on MDM9615 uses external CXO and PLL7
clocks. Split the qcom,gcc-mdm9615 to the separate schema file.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230512211727.3445575-4-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-31 14:24:04 -07:00
Dmitry Baryshkov
9f08d33496 dt-bindings: clock: drop qcom,lcc-mdm9615 header file 
The header file for qcom,lcc-mdm9615 and qcom,lcc-msm8960 is the same
(as well as the drivers). Drop the qcom,lcc-mdm9615.h in favour of
qcom,lcc-msm8960.h

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230512211727.3445575-3-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-31 14:23:19 -07:00
Dmitry Baryshkov
83490976a7 dt-bindings: clock: qcom,lcc.yaml: describe clocks for lcc,qcom-mdm9615 
Describe parent clocks used by the LCC on the MDM9615 platform. It is
the list as the one for msm8960/apq8064, with only difference being
pxo/cxo replacement.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230512211727.3445575-2-dmitry.baryshkov@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-31 14:23:19 -07:00
Konrad Dybcio
e5e527d1ed clk: qcom: videocc-sm8350: Add SC8280XP support 
SC8280XP, being a partial derivative of SM8350, shares almost the exact
same videocc block. Extend the 8350 driver to support the bigger brother.

The only notable changes are higher possible frequencies on some clocks
and some switcheroo within the XO/sleep registers (probably due to some
different board crystal configuration).

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230703-topic-8280_videocc-v2-2-c88269806269@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-31 14:15:44 -07:00
Konrad Dybcio
dfe488d99d dt-bindings: clock: qcom,sm8350-videocc: Add SC8280XP 
SC8280XP reuses the SM8350 video clock controller block, changing just a
couple tunables. Docuemnt it.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230703-topic-8280_videocc-v2-1-c88269806269@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-31 14:15:44 -07:00
Konrad Dybcio
20e1d75bc0 clk: qcom: dispcc-sc8280xp: Use ret registers on GDSCs 
The DISP_CC GDSCs have not been instructed to use the ret registers.
Fix that.

Fixes: 4a66e76fdb ("clk: qcom: Add SC8280XP display clock controller")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230725-topic-8280_dispcc_gdsc-v1-1-236590060531@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-27 20:28:15 -07:00
Johan Hovold
a9f71a0335 clk: qcom: turingcc-qcs404: fix missing resume during probe 
Drivers that enable runtime PM must make sure that the controller is
runtime resumed before accessing its registers to prevent the power
domain from being disabled.

Fixes: 892df0191b ("clk: qcom: Add QCS404 TuringCC")
Cc: stable@vger.kernel.org      # 5.2
Cc: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20230718132902.21430-9-johan+linaro@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-18 07:58:50 -07:00
Johan Hovold
e2349da0fa clk: qcom: mss-sc7180: fix missing resume during probe 
Drivers that enable runtime PM must make sure that the controller is
runtime resumed before accessing its registers to prevent the power
domain from being disabled.

Fixes: 8def929c40 ("clk: qcom: Add modem clock controller driver for SC7180")
Cc: stable@vger.kernel.org      # 5.7
Cc: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20230718132902.21430-8-johan+linaro@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-18 07:58:50 -07:00
Johan Hovold
97112c83f4 clk: qcom: q6sstop-qcs404: fix missing resume during probe 
Drivers that enable runtime PM must make sure that the controller is
runtime resumed before accessing its registers to prevent the power
domain from being disabled.

Fixes: 6cdef2738d ("clk: qcom: Add Q6SSTOP clock controller for QCS404")
Cc: stable@vger.kernel.org      # 5.5
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20230718132902.21430-7-johan+linaro@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-18 07:58:50 -07:00
Johan Hovold
66af5339d4 clk: qcom: lpasscc-sc7280: fix missing resume during probe 
Drivers that enable runtime PM must make sure that the controller is
runtime resumed before accessing its registers to prevent the power
domain from being disabled.

Fixes: 4ab43d1711 ("clk: qcom: Add lpass clock controller driver for SC7280")
Cc: stable@vger.kernel.org      # 5.16
Cc: Taniya Das <quic_tdas@quicinc.com>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20230718132902.21430-6-johan+linaro@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-18 07:58:50 -07:00
Johan Hovold
10192ab375 clk: qcom: gcc-sc8280xp: fix runtime PM imbalance on probe errors 
Make sure to decrement the runtime PM usage count before returning in
case RCG dynamic frequency switch initialisation fails.

Fixes: 2a541abd98 ("clk: qcom: gcc-sc8280xp: Add runtime PM")
Cc: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Link: https://lore.kernel.org/r/20230718132902.21430-5-johan+linaro@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-07-18 07:58:49 -07:00