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Author SHA1 Message Date
Konrad Dybcio
a74883a0de arm64: dts: qcom: sa8775p: Hook up PDC as wakeup-parent of TLMM 
Some TLMM pins are wakeup-capable. Describe the relationship between
these two peripherals to enable this functionality.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230811-topic-tlmm_wakeup-v1-4-5616a7da1fff@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-15 09:35:33 -07:00
Konrad Dybcio
57ff519a64 arm64: dts: qcom: sc8280xp: Hook up PDC as wakeup-parent of TLMM 
Some TLMM pins are wakeup-capable. Describe the relationship between
these two peripherals to enable this functionality.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230811-topic-tlmm_wakeup-v1-3-5616a7da1fff@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-15 09:35:33 -07:00
Konrad Dybcio
b51ee205dc arm64: dts: qcom: sdm670: Add PDC 
Add support for the PDC to enable deep sleep wakeup from external sources.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230811-topic-tlmm_wakeup-v1-2-5616a7da1fff@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-15 09:35:33 -07:00
Lin, Meng-Bo
befa79798a arm64: dts: qcom: msm8916-samsung-e5: Add touchscreen 
Similar to A5, E5 uses a Melfas MMS345L touchscreen that is connected to
blsp_i2c5. Add it to the device tree.

Signed-off-by: Lin, Meng-Bo <linmengbo0689@protonmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230812071448.4710-1-linmengbo0689@protonmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:29:48 -07:00
Nikita Travkin
4fb40b22e9 arm64: dts: qcom: sc7180: Split up TF-A related PSCI configuration 
When initially submitted, the sc7180 support only targeted CROS devices
that make use of alternative TF-A firmware and not the official Qualcomm
firmware. The PSCI implementations in those firmwares differ however so
devices that use qcom firmware, like WoA laptops such as aspire1 need
different setup.

This commit adjusts the SoC dtsi to the OSI mode PSCI setup, common to
the Qualcomm firmware and introduces new sc7180-firmware-tfa.dtsi that
overrides the PSCI setup for the PC mode and uses TF-A specific
psci-suspend-param. This dtsi is added to all boards that appear to use
TF-A.

Signed-off-by: Nikita Travkin <nikita@trvn.ru>
Link: https://lore.kernel.org/r/20230808-sc7180-tfa-fw-v1-1-666d5d8467e5@trvn.ru
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:19:02 -07:00
Konrad Dybcio
1c63dd1c5f arm64: dts: qcom: sc8280xp-x13s: Add camera activity LED 
Disappointigly, the camera activity LED is implemented in software.
Hook it up as a gpio-led and (until we have camera *and* a "camera on"
LED trigger) configure it as a panic indicator.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230805-topic-x13s_cam_led-v1-1-443d752158c4@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:12:37 -07:00
Konrad Dybcio
7868ed0144 arm64: dts: qcom: sc8280xp-x13s: Unreserve NC pins 
Pins 83-86 and 158-160 are NC, so there's no point in keeping them
reserved. Take care of that.

Fixes: 32c231385e ("arm64: dts: qcom: sc8280xp: add Lenovo Thinkpad X13s devicetree")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230803-topic-x13s_pin-v1-1-fae792274e89@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:12:32 -07:00
AngeloGioacchino Del Regno
ff88e1c9dd arm64: dts: qcom: msm8998: Add DPU1 nodes 
Add the required nodes to support the display hardware on msm8998.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
[konrad: update the commit msg and AGdR's email, rebase]
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230805-topic-8998_dpu-v1-1-9d402dc1ecc0@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:12:01 -07:00
David Wronek
bd3b4ac118 arm64: dts: qcom: msm8996: Fix dsi1 interrupts 
Fix IRQ flags mismatch which was keeping dsi1 from probing by changing
interrupts = <4> to interrupts = <5>.

Fixes: 2752bb7d9b ("arm64: dts: qcom: msm8996: add second DSI interface")
Signed-off-by: David Wronek <davidwronek@gmail.com>
Acked-by: Yassine Oudjana <y.oudjana@protonmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230805130936.359860-2-davidwronek@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:11:59 -07:00
Rohit Agarwal
8a2dc39d10 arm64: dts: qcom: sdx75-idp: Add regulator nodes 
Add all the regulators along with labels found on SDX75 IDP.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/1691415534-31820-10-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:11:57 -07:00
Rohit Agarwal
1862d0e3eb arm64: dts: qcom: sdx75: Add rpmhpd node 
Add rpmhpd node and opps for this node to the SDX75 dts.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/1691415534-31820-9-git-send-email-quic_rohiagar@quicinc.com
[bjorn: include qcom-rpmpd.h as well]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:11:16 -07:00
Rohit Agarwal
f890ef1864 arm64: dts: qcom: sdx75-idp: Add pmics supported in SDX75 
SDX75-idp features pmk8550, pmx75 and pm7550ba pmic, so include them.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/1691415534-31820-8-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:05:06 -07:00
Rohit Agarwal
0d64992d85 arm64: dts: qcom: Add pmx75 PMIC dtsi 
Add dtsi for pmx75 PMIC found in Qualcomm platforms.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/1691415534-31820-6-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:05:06 -07:00
Rohit Agarwal
5f78e80ca7 arm64: dts: qcom: Add pm7550ba PMIC dtsi 
Add dtsi for pm7550ba PMIC found in Qualcomm platforms.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Link: https://lore.kernel.org/r/1691415534-31820-5-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:05:06 -07:00
Rohit Agarwal
e99a7a0c85 arm64: dts: qcom: Add pinctrl gpio support for pm7250b 
Add pinctrl gpio dts node for pm7250b.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/1691415534-31820-4-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:05:06 -07:00
Rohit Agarwal
1020fca4f2 arm64: dts: qcom: sdx75: Add spmi node 
Add SPMI node to SDX75 dtsi.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/1691415534-31820-3-git-send-email-quic_rohiagar@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:05:06 -07:00
Konrad Dybcio
7f828f3207 arm64: dts: qcom: msm8998: Add missing power domain to MMSS SMMU 
The MMSS SMMU has its own power domain. Attach it so that we can drop
the "keep it always-on" hack.

Fixes: 05ce21b544 ("arm64: dts: qcom: msm8998: Configure the multimedia subsystem iommu")
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230531-topic-8998_mmssclk-v3-2-ba1b1fd9ee75@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:01:53 -07:00
Konrad Dybcio
a3ce236364 arm64: dts: qcom: msm8998: Drop bus clock reference from MMSS SMMU 
The MMSS SMMU has been abusingly consuming the exposed RPM interconnect
clock. Drop it.

Fixes: 05ce21b544 ("arm64: dts: qcom: msm8998: Configure the multimedia subsystem iommu")
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230531-topic-8998_mmssclk-v3-1-ba1b1fd9ee75@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:01:53 -07:00
Konrad Dybcio
6578747ae2 arm64: dts: qcom: sm8450: Add RPMh stats 
SM8450 also exposes RPMh stats, hook them up for low power state
monitoring.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230811-topic-8450_stats-v1-1-f26ae3fdf2cf@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 20:01:12 -07:00
Konrad Dybcio
63f4e4b447 arm64: dts: qcom: msm8998: Use the correct GPLL0_DIV leg for MMCC 
MMCC has its own GPLL0 legs - one for 1-1 and one for div-2 output.
We've already been using the correct one in the non-div case, start
doing so for the other one as well.

Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-8-6222fbc2916b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 19:52:09 -07:00
Konrad Dybcio
00ada6afea arm64: dts: qcom: msm8998: Use the correct GPLL0 leg for GPUCC 
GPUCC has its own GPLL0 leg, switch to it to allow shutting it down
when it's unused.

Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-7-6222fbc2916b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 19:52:09 -07:00
Bjorn Andersson
9328ecb29d Merge branch '20230622-topic-8998clk-v2-1-6222fbc2916b@linaro.org' into arm64-for-6.6 
Merge additional MSM8998 GCC DeviceTree binding constants for use in the
MSM8998 DeviceTree source.
 2023-08-13 19:51:26 -07:00
Konrad Dybcio
238e192bed dt-bindings: clk: qcom,gcc-msm8998: Add missing GPU/MMSS GPLL0 legs 
GPLL0 has two separate outputs to both GPUSS and MMSS: one that's
2-divided and one that runs at the same rate as the GPLL0 itself.

Add the missing ones to the binding.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230622-topic-8998clk-v2-1-6222fbc2916b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 19:49:47 -07:00
Sridharan S N
0354e2d4d2 arm64: dts: qcom: ipq5332: enable GPIO based LEDs and Buttons 
Add support for wlan-2g LED on GPIO 36 and wps buttons on GPIO 35.

Signed-off-by: Sridharan S N <quic_sridsn@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230616083238.20690-2-quic_sridsn@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 19:48:36 -07:00
Konrad Dybcio
76a6dd7bfc arm64: dts: qcom: sm8450: Add PRNG 
Add the Qualcomm Pseudo-Random Number Generator.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230811-topic-8450_prng-v1-3-01becceeb1ee@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 19:39:44 -07:00
Bryan O'Donoghue
c27c73bb56 arm64: dts: qcom: apq8016-sbc: Enable camss for non-mezzanine cases 
When we have no camera mezzanine attached it is still possible to run the
test-pattern generator of the CSID block.

As an example:

media-ctl --reset

yavta --no-query -w '0x009f0903 1' /dev/v4l-subdev2
yavta --list /dev/v4l-subdev2

media-ctl -d /dev/media0 -V '"msm_csid0":0[fmt:UYVY8_1X16/1920x1080 field:none]'
media-ctl -l '"msm_csid0":1->"msm_ispif0":0[1]'
media-ctl -d /dev/media0 -V '"msm_ispif0":0[fmt:UYVY8_1X16/1920x1080 field:none]'
media-ctl -l '"msm_ispif0":1->"msm_vfe0_rdi0":0[1]'
media-ctl -d /dev/media0 -V '"msm_vfe0_rdi0":0[fmt:UYVY8_1X16/1920x1080]'
media-ctl -d /dev/media0 -p

yavta -B capture-mplane --capture=5 -n 5 -I -f UYVY -s 1920x1080 --file=TPG-UYVU-1920x1080-000-#.bin /dev/video0

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20230811234738.2859417-8-bryan.odonoghue@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 19:38:32 -07:00
Bryan O'Donoghue
6823df3158 arm64: dts: qcom: apq8016-sbc-d3-camera-mezzanine: Move default ov5640 to a standalone dts 
At the moment we define a single ov5640 sensor in the apq8016-sbc and
disable that sensor.

The sensor mezzanine for this is a D3 Engineering Dual ov5640 mezzanine
card. Move the definition from the apq8016-sbc where it shouldn't be to a
standalone dts.

Enables the sensor by default, as we are adding a standalone mezzanine
structure.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230811234738.2859417-7-bryan.odonoghue@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 19:38:32 -07:00
Bryan O'Donoghue
4facccb44a arm64: dts: qcom: apq8016-sbc: Rename ov5640 enable-gpios to powerdown-gpios 
There are two control lines controlled by GPIO going into ov5640

- Reset
- Powerdown

The driver and yaml expect "reset-gpios" and "powerdown-gpios" there has
never been an "enable-gpios".

Fixes: 39e0ce6cd1 ("arm64: dts: qcom: apq8016-sbc: Add CCI/Sensor nodes")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230811234738.2859417-6-bryan.odonoghue@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 19:38:32 -07:00
Bryan O'Donoghue
775d2f3f76 arm64: dts: qcom: apq8016-sbc: Set ov5640 assigned-clock 
The driver for the ov5640 doesn't do a set-rate, instead it expects the
clock to already be set at an appropriate rate.

Similarly the yaml for ov5640 doesn't understand clock-frequency. Convert
from clock-rate to assigned-clock and assigned-clock-rate to remediate.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230811234738.2859417-5-bryan.odonoghue@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 19:38:32 -07:00
Bryan O'Donoghue
3652866ff4 arm64: dts: qcom: apq8016-sbc: Fix ov5640 data-lanes declaration 
The yaml constraint for data-lanes is [1, 2] not [0, 2]. The driver itself
doesn't do anything with the data-lanes declaration save count the number
of specified data-lanes and calculate the link rate so, this change doesn't
have any functional side-effects.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20230811234738.2859417-4-bryan.odonoghue@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 19:38:32 -07:00
Bryan O'Donoghue
43a6845808 arm64: dts: qcom: apq8016-sbc: Fix ov5640 regulator supply names 
The ov5640 driver expects DOVDD, AVDD and DVDD as regulator supply names.

The ov5640 has depended on these names since the driver was committed
upstream in 2017. Similarly apq8016-sbc.dtsi has had completely different
regulator names since its own initial commit in 2020.

Perhaps the regulators were left on in previous 410c bootloaders. In any
case today on 6.5 we won't switch on the ov5640 without correctly naming
the regulators.

Fixes: 39e0ce6cd1 ("arm64: dts: qcom: apq8016-sbc: Add CCI/Sensor nodes")
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230811234738.2859417-3-bryan.odonoghue@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 19:38:32 -07:00
Bryan O'Donoghue
349a13a1e7 arm64: dts: qcom: msm8916: Define CAMSS ports in core dtsi 
Each CSIPHY in CAMMS maps to a port here in the dtsi, since the number of
CSIPHYs is fixed per SoC define the 8916 ports for both available PHYs.

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230811234738.2859417-2-bryan.odonoghue@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-13 19:38:32 -07:00
Sricharan Ramabadhran
570006756a arm64: dts: Add ipq5018 SoC and rdp432-c2 board support 
Add initial device tree support for the Qualcomm IPQ5018 SoC and
rdp432-c2 board.

Few things like 'reboot' does not work because, couple of more 'SCM'
APIS are needed to clear some TrustZone settings. Those will be
posted separately.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Co-developed-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Signed-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/r/1690533192-22220-6-git-send-email-quic_srichara@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-11 10:55:09 -07:00
Sricharan Ramabadhran
f810050479 dt-bindings: qcom: Add ipq5018 bindings 
Document the new ipq5018 SOC/board device tree bindings.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/r/1690533192-22220-4-git-send-email-quic_srichara@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-11 10:55:09 -07:00
Bjorn Andersson
c02a547da3 Merge branch '1690533192-22220-2-git-send-email-quic_srichara@quicinc.com' into arm64-for-6.6 
Merge the IPQ5018 GCC Devicetree binding through a topic branch, in
order to the the clock defines.
 2023-08-11 10:51:15 -07:00
Sricharan Ramabadhran
f62d184ef7 dt-bindings: clock: Add IPQ5018 clock and reset 
This patch adds support for the global clock controller found on
the IPQ5018 based devices.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/r/1690533192-22220-2-git-send-email-quic_srichara@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-11 10:46:59 -07:00
Bartosz Golaszewski
27eb552ef5 arm64: dts: qcom: sa8775p-ride: enable EMAC1 
Enable the second MAC on sa8775p-ride.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-10-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-11 10:34:06 -07:00
Bartosz Golaszewski
fdc051e392 arm64: dts: qcom: sa8775p-ride: add an alias for ethernet0 
Once we add a second ethernet node, the MDIO bus names will conflict
unless we provide aliases. Add one for the existing ethernet node.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-9-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-11 10:34:06 -07:00
Bartosz Golaszewski
f8be0c50ce arm64: dts: qcom: sa8775p-ride: sort aliases alphabetically 
For improved readability order the aliases alphabetically for
sa8775p-ride.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Suggested-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-8-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-11 10:34:06 -07:00
Bartosz Golaszewski
1a00a068de arm64: dts: qcom: sa8775p-ride: add the second SGMII PHY 
Add a second SGMII PHY that will be used by EMAC1 on sa8775p-ride.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-7-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-11 10:34:06 -07:00
Bartosz Golaszewski
1e7ef41b5f arm64: dts: qcom: sa8775p-ride: index the first SGMII PHY 
We'll be adding a second SGMII PHY on the same MDIO bus, so let's index
the first one for better readability.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-6-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-11 10:34:05 -07:00
Bartosz Golaszewski
5255901fb2 arm64: dts: qcom: sa8775p-ride: move the reset-gpios property of the PHY 
Device-tree bindings for MDIO define per-PHY reset-gpios as well as a
global reset-gpios property at the MDIO node level which controls all
devices on the bus. The latter is most likely a workaround for the
chicken-and-egg problem where we cannot read the ID of the PHY before
bringing it out of reset but we cannot bring it out of reset until we've
read its ID.

I have proposed a comprehensive solution for this problem in 2020 but it
never got upstream. We do however have workaround in place which allows
us to hard-code the PHY id in the compatible property, thus skipping the
ID scanning.

Let's make the device-tree for sa8775p-ride slightly more correct by
moving the reset-gpios property to the PHY node with its ID put into the
PHY node's compatible.

Link: https://lore.kernel.org/all/20200622093744.13685-1-brgl@bgdev.pl/
Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-5-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-11 10:34:05 -07:00
Bartosz Golaszewski
6ca89cc680 arm64: dts: qcom: sa8775p-ride: enable the second SerDes PHY 
Enable the second SerDes PHY on sa8775p-ride development board.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-4-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-11 10:34:05 -07:00
Bartosz Golaszewski
e952348a7c arm64: dts: qcom: sa8775p: add a node for EMAC1 
Add a node for the second MAC on sa8775p platforms.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-3-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-11 10:34:05 -07:00
Bartosz Golaszewski
31cd8caf0c arm64: dts: qcom: sa8775p: add a node for the second serdes PHY 
Add a node for the SerDes PHY used by EMAC1 on sa8775p-ride.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Reviewed-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com>
Link: https://lore.kernel.org/r/20230810080909.6259-2-brgl@bgdev.pl
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-11 10:34:05 -07:00
Bryan O'Donoghue
5480b0c67f arm64: dts: qcom: sdm845: Enable CAMSS on the bare rb3 board 
Enable CAMSS on the standard RB3 as it is possible to run the test pattern
generator (TPG) without any populated ports/endpoints.

media-ctl --reset
yavta --no-query -w '0x009f0903 9' /dev/v4l-subdev4
yavta --list /dev/v4l-subdev4
media-ctl -d /dev/media0 -V '"msm_csid0":0[fmt:SGRBG10_1X10/3280x2464]'
media-ctl -d /dev/media0 -V '"msm_vfe0_rdi0":0[fmt:SGRBG10_1X10/3280x2464]'
media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]'
media-ctl -d /dev/media0 -p
yavta -B capture-mplane --capture=5 -n 5 -I -f SGRBG10P -s 3280x2464 --file=TPG-SGRBG10-3280x2464-000-#.bin /dev/video2

Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Link: https://lore.kernel.org/r/20230809203534.1100030-2-bryan.odonoghue@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-10 07:22:17 -07:00
Eric Chanudet
e85cbb34f3 arm64: dts: qcom: sa8540p-ride: enable rtc 
SA8540P-ride is one of the Qualcomm platforms that does not have access
to UEFI runtime services and on which the RTC registers are read-only,
as described in:
https://lore.kernel.org/all/20230202155448.6715-1-johan+linaro@kernel.org/

Reserve four bytes in one of the PMIC registers to hold the RTC offset
the same way as it was done for sc8280xp-crd which has similar
limitations:
    commit e67b45582c ("arm64: dts: qcom: sc8280xp-crd: enable rtc")

On SA8540P-ride, the register bank SDAM6 of the first PMIC is not
writable. Following recommendations provided during the review, use
SDAM2 from the second PMIC at offset 0xa0 instead.

Reviewed-by: Caleb Connolly <caleb.connolly@linaro.org>
Signed-off-by: Eric Chanudet <echanude@redhat.com>
Link: https://lore.kernel.org/r/20230809203506.1833205-1-echanude@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-10 07:21:57 -07:00
Richard Acayan
605a981e53 arm64: dts: qcom: sdm670: add frequency profile 
Add the coefficients for the CPU frequencies to aid in frequency
scaling.

Profiling setup:
 - freqbench (https://github.com/kdrag0n/freqbench)
 - LineageOS kernel, android_kernel_google_msm-4.9
 - recommended configuration options by freqbench
 - disabled options that require clang or 32-bit compilers
 - mmc governor switched from simple_ondemand to powersave

    Frequency domains: cpu1 cpu6
    Offline CPUs: cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7
    Sampling power every 1000 ms
    Baseline power usage: 445 mW

    ===== CPU 1 =====
    Frequencies: 300 576 748 998 1209 1324 1516 1612 1708

     300:  1114     3.7 C/MHz     43 mW   11.6 J   25.8 I/mJ   269.4 s
     576:  2138     3.7 C/MHz     51 mW    7.1 J   42.2 I/mJ   140.3 s
     748:  2780     3.7 C/MHz     67 mW    7.3 J   41.3 I/mJ   107.9 s
     998:  3706     3.7 C/MHz     73 mW    5.9 J   51.1 I/mJ    80.9 s
    1209:  4490     3.7 C/MHz     86 mW    5.7 J   52.2 I/mJ    66.8 s
    1324:  4918     3.7 C/MHz     90 mW    5.5 J   54.6 I/mJ    61.0 s
    1516:  5631     3.7 C/MHz    103 mW    5.5 J   54.9 I/mJ    53.3 s
    1612:  5987     3.7 C/MHz    109 mW    5.5 J   55.0 I/mJ    50.1 s
    1708:  6344     3.7 C/MHz    126 mW    5.9 J   50.5 I/mJ    47.3 s

    ===== CPU 6 =====
    Frequencies: 300 652 825 979 1132 1363 1536 1747 1843 1996

     300:  1868     6.2 C/MHz     53 mW    8.5 J   35.2 I/mJ   160.6 s
     652:  4073     6.2 C/MHz     96 mW    7.1 J   42.4 I/mJ    73.7 s
     825:  5132     6.2 C/MHz    117 mW    6.9 J   43.7 I/mJ    58.5 s
     979:  6099     6.2 C/MHz    151 mW    7.4 J   40.4 I/mJ    49.2 s
    1132:  7071     6.2 C/MHz    207 mW    8.8 J   34.1 I/mJ    42.4 s
    1363:  8482     6.2 C/MHz    235 mW    8.3 J   36.1 I/mJ    35.4 s
    1536:  9578     6.2 C/MHz    287 mW    9.0 J   33.3 I/mJ    31.3 s
    1747: 10892     6.2 C/MHz    340 mW    9.4 J   32.0 I/mJ    27.6 s
    1843: 11471     6.2 C/MHz    368 mW    9.6 J   31.1 I/mJ    26.2 s
    1996: 12425     6.2 C/MHz    438 mW   10.6 J   28.3 I/mJ    24.2 s

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Link: https://lore.kernel.org/r/20230802011548.387519-10-mailingradian@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-03 20:47:09 -07:00
Richard Acayan
0c665213d1 arm64: dts: qcom: sdm670: add cpu frequency scaling 
Add CPU frequency scaling, and also add the corresponding memory and
cache bandwidths for each frequency.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Link: https://lore.kernel.org/r/20230802011548.387519-9-mailingradian@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-03 20:47:09 -07:00
Richard Acayan
8cd5597a9b arm64: dts: qcom: sdm670: add osm l3 
Add the interconnect node for L3 cache on SDM670.

Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230802011548.387519-8-mailingradian@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2023-08-03 20:47:09 -07:00