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Dmitry Baryshkov
a06a2f12f9 arm64: dts: qcom: qrb4210-rb2: enable USB-C port handling 
Plug in USB-C related bits and pieces to enable USB role switching and
USB-C orientation handling for the Qualcomm RB2 board.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240130-pmi632-typec-v3-6-b05fe44f0a51@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-09 17:05:59 -06:00
Vladimir Zapolskiy
7e3a1f6470 arm64: dts: qcom: sm6115: drop pipe clock selection 
Stop selecting UTMI clock as the USB3 PIPE clock. This setting is
incompatible with the USB host working in USB3 (SuperSpeed) mode.
While we are at it, also drop the default setting for the port speed.

Fixes: 9dd5f6dba7 ("arm64: dts: qcom: sm6115: Add USB SS qmp phy node")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
[DB: fixed commit message, dropped dr_mode setting]
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Luca Weiss <luca.weiss@fairphone.com> # sdm632-fairphone-fp3
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240130-pmi632-typec-v3-5-b05fe44f0a51@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-09 17:05:42 -06:00
Dmitry Baryshkov
f69b3e40f4 arm64: dts: qcom: pmi632: define USB-C related blocks 
Define VBUS regulator and the Type-C handling block as present on the
Quacomm PMI632 PMIC.

Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Luca Weiss <luca.weiss@fairphone.com> # sdm632-fairphone-fp3
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240130-pmi632-typec-v3-4-b05fe44f0a51@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-09 17:05:41 -06:00
Komal Bajaj
05f439c0e6 arm64: dts: qcom: qcs6490-rb3gen2: Correct the voltage setting for vph_pwr 
Min and max voltages for vph_pwr should be same, otherwise rpmh
will not probe, so correcting the min and max voltages for vph_pwr.

Fixes: 04cf333afc ("arm64: dts: qcom: Add base qcs6490-rb3gen2 board dts")
Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231220110015.25378-3-quic_kbajaj@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-09 11:45:49 -06:00
Komal Bajaj
aa56130e88 arm64: dts: qcom: qcm6490-idp: Correct the voltage setting for vph_pwr 
Min and max voltages for vph_pwr should be same, otherwise rpmh
will not probe, so correcting the min and max voltages for vph_pwr.

Fixes: 9af6a9f32a ("arm64: dts: qcom: Add base qcm6490 idp board dts")
Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231220110015.25378-2-quic_kbajaj@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-09 11:45:49 -06:00
Bjorn Andersson
014bbc990e arm64: dts: qcom: sc8280xp: Introduce additional tsens instances 
The SC8280XP contains two additional tsens instances, providing among
other things thermal measurements for the GPU.

Add these and a GPU thermal-zone.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20240206-sc8280xp-tsens2_3-v3-1-4577b3b38ea8@quicinc.com
[bjorn: s/cpu-crit/gpu-crit/]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 22:42:59 -06:00
Neil Armstrong
31ca6241fe arm64: dts: qcom: sm8550-hdk: correct WCD9385 route and port mapping 
Starting from SM8550, the TX ADC input soundwire port is offset by 1,
and uses the new SWR_INPUTx input ports, so replace the legacy
SWR_ADCx routes for SWR_INPUT0 & SWR_INPUT1 following the correct
TX Soundwire port mapping.

Add some comments on the routing for clarity.

Fixes: b5e25ded27 ("arm64: dts: qcom: sm8550: add support for the SM8550-HDK board")
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240201-topic-sm8550-hdk8550-audio-fix-v1-1-aa526c9c91d5@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 17:54:41 -06:00
Manivannan Sadhasivam
0f9b8054bb arm64: dts: qcom: sm8650: Fix UFS PHY clocks 
QMP PHY used in SM8650 requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from TCSR

Fixes: 10e0246712 ("arm64: dts: qcom: sm8650: add interconnect dependent device nodes")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-17-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 17:54:41 -06:00
Manivannan Sadhasivam
746ae23ad0 arm64: dts: qcom: sm8550: Fix UFS PHY clocks 
QMP PHY used in SM8550 requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from TCSR

Fixes: 35cf1aaab1 ("arm64: dts: qcom: sm8550: Add UFS host controller and phy nodes")
Reviewed-by: Can Guo <quic_cang@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-16-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 17:54:41 -06:00
Manivannan Sadhasivam
8edbdefee1 arm64: dts: qcom: sm8350: Fix UFS PHY clocks 
QMP PHY used in SM8350 requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC

While at it, let's move 'clocks' property before 'clock-names' to match
the style used commonly.

Fixes: 59c7cf8147 ("arm64: dts: qcom: sm8350: Add UFS nodes")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-15-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 17:54:41 -06:00
Manivannan Sadhasivam
1d4ef9644e arm64: dts: qcom: sc8280xp: Fix UFS PHY clocks 
QMP PHY used in SC8280XP requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC

Fixes: 152d1faf1e ("arm64: dts: qcom: add SC8280XP platform")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-14-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 17:54:41 -06:00
Manivannan Sadhasivam
dde7714022 arm64: dts: qcom: sc8180x: Fix UFS PHY clocks 
QMP PHY used in SC8180X requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC

Fixes: 8575f197b0 ("arm64: dts: qcom: Introduce the SC8180x platform")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-13-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 17:54:41 -06:00
Bjorn Andersson
cc2bc7a7ab Merge branch '20240131-ufs-phy-clock-v3-3-58a49d2f4605@linaro.org' into HEAD 
Merge clock topic branch that introduces the SC8180X CLK_REF enable
clocks.
 2024-02-06 17:54:05 -06:00
Manivannan Sadhasivam
55ee02b10b arm64: dts: qcom: sm8250: Fix UFS PHY clocks 
QMP PHY used in SM8250 requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC

While at it, let's move 'clocks' property before 'clock-names' to match
the style used commonly.

Fixes: b7e2fba066 ("arm64: dts: qcom: sm8250: Add UFS controller and PHY")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-12-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:18:38 -06:00
Manivannan Sadhasivam
eff7496b72 arm64: dts: qcom: sm8150: Fix UFS PHY clocks 
QMP PHY used in SM8150 requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC

While at it, let's move 'clocks' property before 'clock-names' to match
the style used commonly.

Fixes: 3834a2e922 ("arm64: dts: qcom: sm8150: Add ufs nodes")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-11-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:18:38 -06:00
Manivannan Sadhasivam
68f9fcba3a arm64: dts: qcom: sm6350: Fix UFS PHY clocks 
QMP PHY used in SM6350 requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC

While at it, let's move 'clocks' property before 'clock-names' to match
the style used commonly.

Fixes: 5a814af5fc ("arm64: dts: qcom: sm6350: Add UFS nodes")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-10-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:18:38 -06:00
Manivannan Sadhasivam
3823a877f2 arm64: dts: qcom: sm6125: Fix UFS PHY clocks 
QMP PHY used in SM6125 requires 3 clocks:

* ref - 19.2MHz reference clock from RPM
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC

Fixes: f8399e8a2f ("arm64: dts: qcom: sm6125: Add UFS nodes")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-9-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:18:38 -06:00
Manivannan Sadhasivam
a820a285ef arm64: dts: qcom: sm6115: Fix UFS PHY clocks 
QMP PHY used in SM6115 requires 3 clocks:

* ref - 19.2MHz reference clock from RPM
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC

Fixes: 97e563bf5b ("arm64: dts: qcom: sm6115: Add basic soc dtsi")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-8-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:18:38 -06:00
Manivannan Sadhasivam
ca8fb2bd22 arm64: dts: qcom: sdm845: Fix UFS PHY clocks 
QMP PHY used in SDM845 requires 3 clocks:

* ref - 19.2MHz reference clock from RPMh
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC

While at it, let's move 'clocks' property before 'clock-names' to match
the style used commonly.

Fixes: cc16687fbd ("arm64: dts: qcom: sdm845: add UFS controller")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-7-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:18:38 -06:00
Manivannan Sadhasivam
5e653a7ff4 arm64: dts: qcom: msm8998: Fix UFS PHY clocks 
QMP PHY used in MSM8998 requires 3 clocks:

* ref - 19.2MHz reference clock from RPM
* ref_aux - Auxiliary reference clock from GCC
* qref - QREF clock from GCC

Fixes: cd3dbe2a4e ("arm64: dts: qcom: msm8998: Add UFS nodes")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-6-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:18:38 -06:00
Manivannan Sadhasivam
c83fdb4335 arm64: dts: qcom: msm8996: Fix UFS PHY clocks 
QMP PHY used in MSM8996 requires 2 clocks:

* ref - 19.2MHz reference clock from RPM
* qref - QREF clock from GCC

Fixes: 27520210e8 ("arm64: dts: qcom: msm8996: Use generic QMP driver for UFS")
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-5-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:18:37 -06:00
Manivannan Sadhasivam
26447dad81 dt-bindings: clock: qcom: Add missing UFS QREF clocks 
Add missing QREF clocks for UFS MEM and UFS CARD controllers.

Fixes: 0fadcdfdcf ("dt-bindings: clock: Add SC8180x GCC binding")
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20240131-ufs-phy-clock-v3-3-58a49d2f4605@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:11:03 -06:00
Christian Marangi
cb77d0ad46 arm64: dts: qcom: ipq8074: add clock-frequency to MDIO node 
Add clock-frequency to MDIO node to set the MDC rate to 6.25Mhz instead
of using the default value of 390KHz from MDIO default divider.

Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240131022731.2118-1-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:09:39 -06:00
Dmitry Baryshkov
7f492d48f0 arm64: dts: qcom: qrb2210-rb1: disable cluster power domains 
If cluster domain idle state is enabled on the RB1, the board becomes
significantly less responsive. Under certain circumstances (if some of
the devices are disabled in kernel config) the board can even lock up.

It seems this is caused by the MPM not updating wakeup timer during CPU
idle (in the same way the RPMh updates it when cluster idle state is
entered).

Disable cluster domain idle for the RB1 board until MPM driver is fixed
to cooperate with the CPU idle states.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240130-rb1-suspend-cluster-v2-1-5bc1109b0869@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:09:26 -06:00
Vladimir Lypak
655815649f arm64: dts: qcom: msm8953: Add GPU 
Add the GPU node for the Adreno 506 found on this family of SoCs. The
clock speeds are a bit different per SoC variant, SDM450 maxes out at
600MHz while MSM8953 (= SDM625) goes up to 650MHz and SDM632 goes up to
725MHz.

To achieve this, create a new sdm450.dtsi to hold the 600MHz OPP and
use the new dtsi for sdm450-motorola-ali.

Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Co-developed-by: Luca Weiss <luca@z3ntu.xyz>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240125-msm8953-gpu-v1-2-f6493a5951f3@z3ntu.xyz
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:06:06 -06:00
Vladimir Lypak
1e48ad0d85 arm64: dts: qcom: msm8953: Add GPU IOMMU 
Add the IOMMU used for the GPU on MSM8953.

Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240125-msm8953-gpu-v1-1-f6493a5951f3@z3ntu.xyz
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:06:06 -06:00
Vladimir Lypak
9b4dec638c arm64: dts: qcom: msm8953: add reset for display subsystem 
With this reset we can avoid situations like IRQ storms from DSI host
before it even started probing (because boot-loader left DSI IRQs on).

Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240125-msm8953-mdss-reset-v2-3-fd7824559426@z3ntu.xyz
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:04:54 -06:00
Bjorn Andersson
5ca4cd8eaa Merge branch '20240125-msm8953-mdss-reset-v2-1-fd7824559426@z3ntu.xyz' into arm64-for-6.9 
Merge MSM8953 GCC DeviceTree binding update from topic branch, to get
access to newly introduced MDSS reset constants.
 2024-02-06 16:04:25 -06:00
Vladimir Lypak
18ba9974b8 dt-bindings: clock: gcc-msm8953: add more resets 
Add new defines for some more BCRs found on MSM8953.

Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
[luca: expand commit message, add more resets]
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Link: https://lore.kernel.org/r/20240125-msm8953-mdss-reset-v2-1-fd7824559426@z3ntu.xyz
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:03:26 -06:00
Neil Armstrong
6e9d86933c arm64: dts: qcom: sm8650-mtp: add Audio sound card node 
Add the sound card of SM8650-MTP board with the routing for Speakers.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240125-topic-sm8650-upstream-audio-dt-v1-2-c24d23ae5763@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:02:47 -06:00
Neil Armstrong
ce745475ac arm64: dts: qcom: sm8650-qrd: add Audio nodes 
Add the remaining Audio nodes on the SM8650-QRD board including:
- Qualcomm Aqstic WCD9395 audio codec on the RX & TX Soundwire interfaces
- WSA8845 Left & Right Speakers
- Link the WCD9395 Codec node to the WCD9395 USB SubSystem node to handle
  the USB-C Audio Accessory Mode events & lane swapping
- Sound card with routing for Speakers and Microphones

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240125-topic-sm8650-upstream-audio-dt-v1-1-c24d23ae5763@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:02:47 -06:00
Ling Xu
feed050768 arm64: dts: qcom: sm8650: Add dma-coherent property 
Add dma-coherent property to fastRPC context bank nodes to pass dma
sequence test in fastrpc sanity test, ensure that data integrity is
maintained during DMA operations.

Signed-off-by: Ling Xu <quic_lxu5@quicinc.com>
Link: https://lore.kernel.org/r/20240125102413.3016-3-quic_lxu5@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:00:14 -06:00
Ling Xu
4a03b85b84 arm64: dts: qcom: sm8550: Add dma-coherent property 
Add dma-coherent property to fastRPC context bank nodes to pass dma
sequence test in fastrpc sanity test, ensure that data integrity is
maintained during DMA operations.

Signed-off-by: Ling Xu <quic_lxu5@quicinc.com>
Link: https://lore.kernel.org/r/20240125102413.3016-2-quic_lxu5@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 16:00:14 -06:00
Fenglin Wu
4a8efd8a02 arm64: dts: qcom: sm8650-qrd: add PM8010 regulators 
Add PM8010 regulator device nodes for sm8650-qrd board.

Signed-off-by: Fenglin Wu <quic_fenglinw@quicinc.com>
Reviewed-by: David Collins <quic_collinsd@quicinc.com>
Link: https://lore.kernel.org/r/20240125-sm8650_pm8010_support-v3-2-2f291242a7c4@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 15:59:32 -06:00
Fenglin Wu
a2eb99176b arm64: dts: qcom: sm8650-mtp: add PM8010 regulators 
Add PM8010 regulator device nodes for sm8650-mtp board.

Signed-off-by: Fenglin Wu <quic_fenglinw@quicinc.com>
Reviewed-by: David Collins <quic_collinsd@quicinc.com>
Link: https://lore.kernel.org/r/20240125-sm8650_pm8010_support-v3-1-2f291242a7c4@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 15:59:32 -06:00
Mantas Pucka
8f053e5616 arm64: dts: qcom: ipq6018: add thermal zones 
Add thermal zones to make use of thermal sensors data. For CPU zone,
add cooling device that uses CPU frequency scaling.

Signed-off-by: Mantas Pucka <mantas@8devices.com>
Link: https://lore.kernel.org/r/1706173452-1017-4-git-send-email-mantas@8devices.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 15:58:26 -06:00
Mantas Pucka
0b17197055 arm64: dts: qcom: ipq6018: add tsens node 
IPQ6018 has temperature sensing HW block compatible with IPQ8074. Add
node for it.

Signed-off-by: Mantas Pucka <mantas@8devices.com>
Link: https://lore.kernel.org/r/1706173452-1017-3-git-send-email-mantas@8devices.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 15:58:26 -06:00
Krzysztof Kozlowski
503c0129b3 arm64: dts: qcom: sm8550-mtp: add correct analogue microphones 
Add proper audio routes for onboard analogue microphones AMIC[1345] -
MIC biases and route from TX macro codec to WCD9385 audio codec.

This should bring AMIC1, AMIC2 (headphones), AMIC3, AMIC4 and AMIC5
onboard microphones to work, although was not tested on the hardware.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240124164505.293202-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 15:57:55 -06:00
Krzysztof Kozlowski
e2f1a18747 arm64: dts: qcom: sm8550-qrd: add correct analogue microphones 
Add proper audio routes for onboard analogue microphones AMIC[1345] -
MIC biases and route from TX macro codec to WCD9385 audio codec.

This finally brings AMIC1, AMIC3, AMIC4 and AMIC5 onboard microphones to
work.  AMIC2 (headphones) should be fine well, however it didn't work
during tests, probably because of incomplete USB switch.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240124164505.293202-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 15:57:55 -06:00
Krzysztof Kozlowski
b66966b1bb arm64: dts: qcom: sm8550-mtp: correct WCD9385 TX port mapping 
WCD9385 audio codec TX port mapping was copied form HDK8450, but in fact
it is offset by one.  Correct it to fix recording via analogue
microphones.

The change is based on QRD8550 and should be correct here as well, but
was not tested on MTP8550.

Cc: stable@vger.kernel.org
Fixes: a541667c86 ("arm64: dts: qcom: sm8550-mtp: add WCD9385 audio-codec")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240124164505.293202-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 15:57:55 -06:00
Krzysztof Kozlowski
8ca7fbd92c arm64: dts: qcom: sm8550-qrd: correct WCD9385 TX port mapping 
WCD9385 audio codec TX port mapping was copied form HDK8450, but in fact
it is offset by one.  Correct it to fix recording via analogue
microphones.

Cc: stable@vger.kernel.org
Fixes: 83fae950c9 ("arm64: dts: qcom: sm8550-qrd: add WCD9385 audio-codec")
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240124164505.293202-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 15:57:55 -06:00
Luca Weiss
646287950b arm64: dts: qcom: sm6350: Add tsens thermal zones 
Add the definitions for the various thermal zones found on the SM6350
SoC. Hooking up GPU and CPU cooling can limit the clock speeds there to
reduce the temperature again to good levels.

Most thermal zones only have one critical temperature configured at
125°C which can be mostly considered a placeholder until those zones can
be hooked up to cooling.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20240124-sm6350-tsens-v1-1-d37ec82140af@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 15:57:11 -06:00
Dmitry Baryshkov
95d739ed96 arm64: dts: qcom: sm6115: declare VLS CLAMP register for USB3 PHY 
The USB3 PHY on the SM6115 platform doesn't have built-in
PCS_MISC_CLAMP_ENABLE register. Instead clamping is handled separately
via the register in the TCSR space. Declare corresponding register.

Fixes: 9dd5f6dba7 ("arm64: dts: qcom: sm6115: Add USB SS qmp phy node")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240117-usbc-phy-vls-clamp-v2-6-a950c223f10f@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 15:55:48 -06:00
Dmitry Baryshkov
acb94d67f5 arm64: dts: qcom: qcm2290: declare VLS CLAMP register for USB3 PHY 
The USB3 PHY on the QCM2290 platform doesn't have built-in
PCS_MISC_CLAMP_ENABLE register. Instead clamping is handled separately
via the register in the TCSR space. Declare corresponding register.

Fixes: 0c55f6229b ("arm64: dts: qcom: qcm2290: Add USB3 PHY")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20240117-usbc-phy-vls-clamp-v2-5-a950c223f10f@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 15:55:48 -06:00
Dmitry Baryshkov
fc835b2311 arm64: dts: qcom: msm8998: declare VLS CLAMP register for USB3 PHY 
The USB3 PHY on the MSM8998 platform doesn't have built-in
PCS_MISC_CLAMP_ENABLE register. Instead clamping is handled separately
via the register in the TCSR space. Declare corresponding register.

Fixes: 026dad8f58 ("arm64: dts: qcom: msm8998: Add USB-related nodes")
Cc: Jeffrey Hugo <quic_jhugo@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Link: https://lore.kernel.org/r/20240117-usbc-phy-vls-clamp-v2-4-a950c223f10f@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 15:55:48 -06:00
Maulik Shah
db5d137e81 arm64: dts: qcom: sc7280: Update domain-idle-states for cluster sleep 
QCM6490 uses Trustzone as firmware whereas SC7280 uses arm trusted firmware.
The PSCI suspend param and the number of domain-idle-states supported is
different in Trustzone for cluster sleep.

Move the arm trusted firmware supported domain-idle-states in chrome specific
sc7280-chrome-common.dtsi and add the Trustzone supported sleep states as default
domain-idle-states in sc7280.dtsi

Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com>
Link: https://lore.kernel.org/r/20240109-qcm6490_cluster_sleep-v2-1-8f94f1ad188d@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 15:54:43 -06:00
Marijn Suijten
749c47ad33 arm64: dts: qcom: sdm630-nile: Enable and configure PM660L WLED 
The board-specific (electrical) configuration was removed from PM660L in
90ba636e40 ("arm64: dts: qcom: pm660l: Remove board-specific WLED
configuration") as it is platform-dependent.  We reintroduce it here in
the Nile board configuration (with a slightly lower current limit, as
per downstream DT sources) and enable it for use in the dsi0 node.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/r/20240204-sdm630-nile-wled-v1-1-9f5c4f8147f2@somainline.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 15:53:09 -06:00
Dmitry Baryshkov
869c3d4eef dt-bindings: arm: qcom: drop the superfluous device compatibility schema 
The idea impressed in the commit b32e592d3c ("devicetree: bindings:
Document qcom board compatible format") never got actually adopted. As
can be seen from the existing board DT files, no device actually used
the PMIC / foundry / version parts of the compatible string. Drop this
compatibility string description to avoid possible confusion and keep
just the generic terms and the SoC list.

Fixes: b32e592d3c ("devicetree: bindings: Document qcom board compatible format")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20240204-qcom-drop-compat-v1-1-69d6cd92aa0e@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 15:52:14 -06:00
Neil Armstrong
af53ecef19 arm64: dts: qcom: sm8650: add missing qlink_logging reserved memory for mpss 
The qlink_logging memory region is also used by the modem firmware,
add it to the reserved memories and add it to the MPSS memory regions.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Mukesh Ojha <quic_mojha@quicinc.com>
Link: https://lore.kernel.org/r/20240123-topic-sm8650-upstream-remoteproc-v7-4-61283f50162f@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 15:38:56 -06:00
Vignesh Viswanathan
2ae5e34d93 arm64: dts: qcom: ipq9574: Enable Inline Crypto Engine for MMC 
Add Inline Crypto Engine reg and clocks in MMC node and enable CQE
support as Inline Crypto Engine requires CQE to be enabled.

Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Link: https://lore.kernel.org/r/20231215095339.3055554-1-quic_viswanat@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2024-02-06 14:58:57 -06:00