Commit Graph

1308808 Commits

Author SHA1 Message Date
Bjorn Andersson
98e5b7f983 drm/msm/adreno: Setup SMMU aparture for per-process page table
Support for per-process page tables requires the SMMU aparture to be
setup such that the GPU can make updates with the SMMU. On some targets
this is done statically in firmware, on others it's expected to be
requested in runtime by the driver, through a SCM call.

One place where configuration is expected to be done dynamically is the
QCS6490 rb3gen2.

The downstream driver does this unconditioanlly on any A6xx and newer,
so follow suite and make the call.

Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Link: https://lore.kernel.org/r/20241110-adreno-smmu-aparture-v2-2-9b1fb2ee41d4@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-11 12:03:27 -06:00
Bjorn Andersson
1af75b2ad0 firmware: qcom: scm: Introduce CP_SMMU_APERTURE_ID
The QCOM_SCM_SVC_MP service provides QCOM_SCM_MP_CP_SMMU_APERTURE_ID,
which is used to trigger the mapping of register banks into the SMMU
context for per-processes page tables to function (in case this isn't
statically setup by firmware).

This is necessary on e.g. QCS6490 Rb3Gen2, in order to avoid "CP | AHB
bus error"-errors from the GPU.

Introduce a function to allow the msm driver to invoke this call.

Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Link: https://lore.kernel.org/r/20241110-adreno-smmu-aparture-v2-1-9b1fb2ee41d4@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-11 12:03:26 -06:00
Manikanta Mylavarapu
a8fc655e01 soc: qcom: socinfo: add IPQ5424/IPQ5404 SoC ID
Add SoC ID for Qualcomm IPQ5424/IPQ5404.

Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241016151528.2893599-3-quic_mmanikan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05 16:44:28 -08:00
Manikanta Mylavarapu
c9cfca9899 dt-bindings: arm: qcom,ids: add SoC ID for IPQ5424/IPQ5404
Add the ID for Qualcomm IPQ5424/IPQ5404 SoC.

Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241016151528.2893599-2-quic_mmanikan@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05 16:43:41 -08:00
Konrad Dybcio
92f3397c8c soc: qcom: llcc: Flip the manual slice configuration condition
Commit c14e64b469 ("soc: qcom: llcc: Support chipsets that can write
to llcc") made the code not configure certain registers on SDM845 due
to firmware security policies. That turned out only to concern SDM845,
but the condition was chosen such that all other entries (for SoCs that
didnot need it) were required to set .need_llcc_cfg = true.

Flip the condition, so the default is "doesn't need the workaround".

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241104-topic-llcc_flip-v1-1-3003c846d131@oss.qualcomm.com
[bjorn: Dropped a few newly added need_llcc_cfg uses]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05 16:13:25 -08:00
Melody Olvera
4cadd10620 dt-bindings: firmware: qcom,scm: Document sm8750 SCM
Document the scm compatible for sm8750 SoC.

Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241021230427.2632466-1-quic_molvera@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05 14:44:25 -08:00
Sibi Sankar
75837f0b2b firmware: qcom: uefisecapp: Allow X1E Devkit devices
Add X1E Devkit to the allowlist.

Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Tested-by: Marc Zyngier <maz@kernel.org>
Tested-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz>
Link: https://lore.kernel.org/r/20241025123227.3527720-3-quic_sibis@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-05 11:50:10 -08:00
Jingyi Wang
584e936fee soc: qcom: llcc: Add LLCC configuration for the QCS8300 platform
Add LLCC configuration for the QCS8300 platform. There is an errata on
LB_CNT information on QCS8300 platform, hardcode num_banks to get the
correct value.

Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241031-qcs8300_llcc-v3-2-bb56952cb83b@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-03 22:07:44 -06:00
Jingyi Wang
a83e18ca83 dt-bindings: cache: qcom,llcc: Document the QCS8300 LLCC
Document the Last Level Cache Controller on QCS8300 platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Link: https://lore.kernel.org/r/20241031-qcs8300_llcc-v3-1-bb56952cb83b@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-03 22:06:56 -06:00
Song Xue
9f85ed1976 soc: qcom: llcc: Add configuration data for QCS615
Add LLCC configuration support for the QCS615 platform.

Signed-off-by: Song Xue <quic_songxue@quicinc.com>
Link: https://lore.kernel.org/r/20241010-add_llcc_support_for_qcs615-v2-2-044432450a75@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-03 22:05:38 -06:00
Song Xue
08e2d7c64e dt-bindings: cache: qcom,llcc: Document the QCS615 LLCC
Document the LLCC on the QCS615 platform.

The QCS615 platform has LLCC as the system cache controller. It
includes 1 LLCC instance and 1 broadcast interface.

Signed-off-by: Song Xue <quic_songxue@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20241010-add_llcc_support_for_qcs615-v2-1-044432450a75@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-03 22:05:18 -06:00
Dmitry Baryshkov
1685f685ff soc: qcom: llcc: add support for SAR2130P and SAR1130P
Implement necessary support for the LLCC control on the SAR1130P and
SAR2130P platforms. These two platforms use different ATTR1_MAX_CAP
shift and also require manual override for num_banks.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241026-sar2130p-llcc-v3-3-2a58fa1b4d12@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-03 22:04:22 -06:00
Dmitry Baryshkov
6dd3f08c72 soc: qcom: llcc: use deciman integers for bit shift values
As pointed out by Konrad Dybcio, we generally should be using decimal
numbers to represent bit positions / bit shifts rather than hex numbers.
Use decimals for consistency.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20241026-sar2130p-llcc-v3-2-2a58fa1b4d12@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-03 22:04:22 -06:00
Dmitry Baryshkov
53b3e2e0c9 dt-bindings: cache: qcom,llcc: document SAR2130P and SAR1130P
Describe the last level cache controller on the SAR2130P and SAR1130P
platforms. They have 2 banks and also a separate register set to control
scratchpad slice.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241026-sar2130p-llcc-v3-1-2a58fa1b4d12@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-11-03 22:04:22 -06:00
Tengfei Fan
d088afa7de soc: qcom: socinfo: add QCS9100 ID
Add the ID for the Qualcomm QCS9100 SoC.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
Link: https://lore.kernel.org/r/20240911-add_qcs9100_support-v2-2-e43a71ceb017@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-29 15:09:02 -05:00
Tengfei Fan
8cbebdfe3e dt-bindings: arm: qcom,ids: add SoC ID for QCS9100
Add the ID for the Qualcomm QCS9100 SoC.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Tengfei Fan <quic_tengfan@quicinc.com>
Link: https://lore.kernel.org/r/20240911-add_qcs9100_support-v2-1-e43a71ceb017@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-29 15:08:49 -05:00
Kyle Deng
8534231e09 dt-bindings: soc: qcom,aoss-qmp: Document the QCS8300 AOSS channel
Document the Always-On Subsystem side channel on the Qualcomm QCS8300
platform for communication with client found on the SoC such as
remoteprocs.

Signed-off-by: Kyle Deng <quic_chunkaid@quicinc.com>
Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20240911-qcs8300_binding-v2-4-de8641b3eaa1@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-29 15:07:12 -05:00
Jingyi Wang
f8b2f38130 dt-bindings: soc: qcom: add qcom,qcs8300-imem compatible
Document qcom,qcs8300-imem compatible. It has child node for debug
purpose.

Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20240911-qcs8300_binding-v2-3-de8641b3eaa1@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-29 15:07:02 -05:00
Zhenhua Huang
fc0dead9b7 dt-bindings: firmware: qcom,scm: document SCM on QCS8300 SoCs
Document scm compatible for the Qualcomm QCS8300 SoC. It is an interface
to communicate to the secure firmware.

Signed-off-by: Zhenhua Huang <quic_zhenhuah@quicinc.com>
Signed-off-by: Jingyi Wang <quic_jingyw@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20240911-qcs8300_binding-v2-2-de8641b3eaa1@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-29 15:07:02 -05:00
Nikunj Kela
558e8b82a5 soc: qcom: socinfo: add support for SA8255P
Add SocInfo support for SA8255P.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
Link: https://lore.kernel.org/r/20240910171534.2412263-3-quic_nkela@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-29 15:05:21 -05:00
Nikunj Kela
729ee76561 dt-bindings: arm: qcom: add the SoC ID for SA8255P
Add the SoC ID entry for SA8255P.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
Link: https://lore.kernel.org/r/20240910171534.2412263-2-quic_nkela@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-29 15:05:10 -05:00
Zhang Zekun
cd8ec43758 soc: qcom: smp2p: Simplify code with dev_err_probe()
Use dev_err_probe() directly in the driver probe phase, and we
don't need to judge if the error code is not equal to -EPROBE_DEFER.
This can simplify the code a bit.

Signed-off-by: Zhang Zekun <zhangzekun11@huawei.com>
Link: https://lore.kernel.org/r/20240909122921.12627-5-zhangzekun11@huawei.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-29 15:04:31 -05:00
Zhang Zekun
876b405004 soc: qcom: smem: Simplify code with dev_err_probe()
Use dev_err_probe() directly in the driver probe phase, and we
don't need to judge if the error code is not equal to -EPROBE_DEFER.
This can simplify the code a bit.

Signed-off-by: Zhang Zekun <zhangzekun11@huawei.com>
Link: https://lore.kernel.org/r/20240909122921.12627-4-zhangzekun11@huawei.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-29 15:04:31 -05:00
Zhang Zekun
454381b523 soc: qcom: rpmh-rsc: Simplify code with dev_err_probe()
Use dev_err_probe() directly in the driver probe phase, and we
don't need to judge if the error code is not equal to -EPROBE_DEFER.
This can simplify the code a bit.

Signed-off-by: Zhang Zekun <zhangzekun11@huawei.com>
Link: https://lore.kernel.org/r/20240909122921.12627-2-zhangzekun11@huawei.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-29 15:04:31 -05:00
Nikunj Kela
e81ee454d7 dt-bindings: soc: qcom: aoss-qmp: document support for SA8255p
Add compatible for AOSS QMP representing support on SA8255p.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
Link: https://lore.kernel.org/r/20240905192328.3778542-1-quic_nkela@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-29 15:03:51 -05:00
Nikunj Kela
b4bd100500 dt-bindings: firmware: qcom,scm: document support for SA8255p
Add a compatible for the SA8255p platform's Secure Channel Manager
firmware interface.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nikunj Kela <quic_nkela@quicinc.com>
Link: https://lore.kernel.org/r/20240905183016.3742735-1-quic_nkela@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-29 15:03:39 -05:00
Dmitry Baryshkov
25136f046b dt-bindings: soc: qcom,aoss-qmp: Add SAR2130P compatible
Document compatible for the Always-On Subsystem on SAR2130P platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241017-sar2130p-soc-v1-1-7f9c204710c3@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22 23:11:05 -05:00
Dmitry Baryshkov
e19bc8b224 dt-bindings: firmware: qcom,scm: Add SAR2130P compatible
Document compatible for the SCM firmware interface on SAR2130P platform.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241017-sar2130p-scm-v1-1-cc74a6b75c94@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22 23:10:58 -05:00
Dmitry Baryshkov
3fa0104ed2 soc: qcom: socinfo: add SoC IDs for SAR1130P and SAR2130P
Add SoC IDs for Qualcomm SAR1130P and SAR2130P platforms.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241018-sar2130p-socinfo-v1-2-b1e97ea963fe@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22 23:10:19 -05:00
Dmitry Baryshkov
3b3214acd7 dt-bindings: arm: qcom,ids: add SoC ID for SAR2130P and SAR1130P
Add the IDs for Qualcomm SAR2130P and SAR1130P platforms.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241018-sar2130p-socinfo-v1-1-b1e97ea963fe@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22 23:10:19 -05:00
Krzysztof Kozlowski
cb0d1c4e9b dt-bindings: soc: qcom: aoss-qmp: Add SM8750
Document compatible for Qualcomm SM8750 SoC Always-on SubSystem (AOSS),
compatible with existing generic fallback.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20241022064214.22868-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22 21:46:54 -05:00
Lijuan Gao
8921bf54bf soc: qcom: socinfo: Add QCS615 SoC ID table entry
Add SoC Info support for the QCS615 platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
Link: https://lore.kernel.org/r/20241022-add_initial_support_for_qcs615-v4-4-0a551c6dd342@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22 21:43:21 -05:00
Lijuan Gao
dbc81e680a dt-bindings: arm: qcom,ids: add SoC ID for QCS615
Add the ID for the Qualcomm QCS615 SoC.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
Link: https://lore.kernel.org/r/20241022-add_initial_support_for_qcs615-v4-2-0a551c6dd342@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22 21:43:21 -05:00
Konrad Dybcio
11cf9a72bc soc: qcom: smem: Fix up kerneldoc
Fix warnings like:

smem.c:504: warning: No description found for return value of 'qcom_smem_alloc'

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241021-topic-smem_kerneldoc-v1-1-4825904a7e25@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-22 15:35:46 -05:00
Aleksandrs Vinarskis
304c250ba1 firmware: qcom: scm: Allow QSEECOM on Dell XPS 13 9345
Allow particular machine accessing eg. efivars.

Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Stefan Schmidt <stefan.schmidt@linaro.org>
Link: https://lore.kernel.org/r/20241003211139.9296-3-alex.vinarskis@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-14 18:45:04 -05:00
Bjorn Andersson
31a95fe085 soc: qcom: pd-mapper: Add QCM6490 PD maps
The QCM6490 is a variant of SC7280, with the usual set of protection
domains, and hence the need for a PD-mapper. In particular USB Type-C
port management and battery management is pmic_glink based.

Add an entry to the kernel, to avoid the need for userspace to provide
this service.

Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241004-qcm6490-pd-mapper-v1-1-d6f4bc3bffa3@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-07 17:01:19 -05:00
Dan Carpenter
78261cb08f soc: qcom: geni-se: fix array underflow in geni_se_clk_tbl_get()
This loop is supposed to break if the frequency returned from
clk_round_rate() is the same as on the previous iteration.  However,
that check doesn't make sense on the first iteration through the loop.
It leads to reading before the start of these->clk_perf_tbl[] array.

Fixes: eddac5af06 ("soc: qcom: Add GENI based QUP Wrapper driver")
Signed-off-by: Dan Carpenter <dan.carpenter@linaro.org>
Link: https://lore.kernel.org/r/8cd12678-f44a-4b16-a579-c8f11175ee8c@stanley.mountain
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05 22:22:42 -05:00
Jérôme de Bretagne
99b2186b2c firmware: qcom: scm: Allow QSEECOM on Microsoft Surface Pro 9 5G
Add the SC8280XP-based Microsoft Surface Pro 9 5G to the allowlist.

Reviewed-by: Konrad Dybcio <konradybcio@kernel.org>
Signed-off-by: Jérôme de Bretagne <jerome.debretagne@gmail.com>
Reviewed-by: Maximilian Luz <luzmaximilian@gmail.com>
Link: https://lore.kernel.org/r/20240908223505.21011-3-jerome.debretagne@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05 22:20:34 -05:00
Krzysztof Kozlowski
cd3a3e60eb soc: qcom: smem_state: simplify locking with guard()
Simplify error handling (less gotos) over locks with guard().

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240822164853.231087-4-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05 22:12:48 -05:00
Krzysztof Kozlowski
6187aaae71 soc: qcom: pbs: simplify locking with guard()
Simplify error handling (less gotos) over locks with guard().

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240822164853.231087-3-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05 22:12:48 -05:00
Krzysztof Kozlowski
35791e5672 qcom: MAINTAINERS: add linux-msm IRC on OFTC
Qualcomm SoC community gathers in #linux-msm channel on OFTC, so mention
it in the maintainer entries.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240821102602.134216-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05 22:12:07 -05:00
Maya Matuszczyk
c6fa2834af firmware: qcom: scm: Allow QSEECOM on Lenovo Yoga Slim 7x
Allow QSEECOM on Lenovo Yoga Slim 7x, to enable accessing EFI variables.

Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240919134421.112643-2-maccraft123mc@gmail.com
[bjorn: Rewrote commit message]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-10-05 21:49:06 -05:00
Julia Lawall
eea73fa08e soc: qcom: qmi: Reorganize kerneldoc parameter names
Reorganize kerneldoc parameter names to match the parameter
order in the function header.

Problems identified using Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Link: https://lore.kernel.org/r/20240930112121.95324-25-Julia.Lawall@inria.fr
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-09-30 22:03:48 -05:00
Konrad Dybcio
20a0a05f40 soc: qcom: llcc: Use designated initializers for LLC settings
The current way of storing the configuration is very much
unmaintainable. Convert the data to use designated initializers to make
it easier both to understand and add/update the slice configuration
data.

Signed-off-by: Konrad Dybcio <quic_kdybcio@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240910-topic-llcc_unwrap-v2-1-f0487c983373@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-09-30 21:44:18 -05:00
Linus Torvalds
9852d85ec9 Linux 6.12-rc1 v6.12-rc1 2024-09-29 15:06:19 -07:00
Linus Torvalds
3f749befb0 x86: kvm: fix build error
The cpu_emergency_register_virt_callback() function is used
unconditionally by the x86 kvm code, but it is declared (and defined)
conditionally:

  #if IS_ENABLED(CONFIG_KVM_INTEL) || IS_ENABLED(CONFIG_KVM_AMD)
  void cpu_emergency_register_virt_callback(cpu_emergency_virt_cb *callback);
  ...

leading to a build error when neither KVM_INTEL nor KVM_AMD support is
enabled:

  arch/x86/kvm/x86.c: In function ‘kvm_arch_enable_virtualization’:
  arch/x86/kvm/x86.c:12517:9: error: implicit declaration of function ‘cpu_emergency_register_virt_callback’ [-Wimplicit-function-declaration]
  12517 |         cpu_emergency_register_virt_callback(kvm_x86_ops.emergency_disable_virtualization_cpu);
        |         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  arch/x86/kvm/x86.c: In function ‘kvm_arch_disable_virtualization’:
  arch/x86/kvm/x86.c:12522:9: error: implicit declaration of function ‘cpu_emergency_unregister_virt_callback’ [-Wimplicit-function-declaration]
  12522 |         cpu_emergency_unregister_virt_callback(kvm_x86_ops.emergency_disable_virtualization_cpu);
        |         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Fix the build by defining empty helper functions the same way the old
cpu_emergency_disable_virtualization() function was dealt with for the
same situation.

Maybe we could instead have made the call sites conditional, since the
callers (kvm_arch_{en,dis}able_virtualization()) have an empty weak
fallback.  I'll leave that to the kvm people to argue about, this at
least gets the build going for that particular config.

Fixes: 590b09b1d8 ("KVM: x86: Register "emergency disable" callbacks when virt is enabled")
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Sean Christopherson <seanjc@google.com>
Cc: Kai Huang <kai.huang@intel.com>
Cc: Chao Gao <chao.gao@intel.com>
Cc: Farrah Chen <farrah.chen@intel.com>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2024-09-29 14:47:33 -07:00
Linus Torvalds
e7ed343658 Merge tag 'mailbox-v6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox
Pull mailbox updates from Jassi Brar:

 - fix kconfig dependencies (mhu-v3, omap2+)

 - use devie name instead of genereic imx_mu_chan as interrupt name
   (imx)

 - enable sa8255p and qcs8300 ipc controllers (qcom)

 - Fix timeout during suspend mode (bcm2835)

 - convert to use use of_property_match_string (mailbox)

 - enable mt8188 (mediatek)

 - use devm_clk_get_enabled helpers (spreadtrum)

 - fix device-id typo (rockchip)

* tag 'mailbox-v6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox:
  mailbox, remoteproc: omap2+: fix compile testing
  dt-bindings: mailbox: qcom-ipcc: Document QCS8300 IPCC
  dt-bindings: mailbox: qcom-ipcc: document the support for SA8255p
  dt-bindings: mailbox: mtk,adsp-mbox: Add compatible for MT8188
  mailbox: Use of_property_match_string() instead of open-coding
  mailbox: bcm2835: Fix timeout during suspend mode
  mailbox: sprd: Use devm_clk_get_enabled() helpers
  mailbox: rockchip: fix a typo in module autoloading
  mailbox: imx: use device name in interrupt name
  mailbox: ARM_MHU_V3 should depend on ARM64
2024-09-29 09:53:04 -07:00
Linus Torvalds
907537f570 Merge tag 'i2c-for-6.12-rc1-additional_fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux
Pull i2c fixes from Wolfram Sang:

 - fix DesignWare driver ENABLE-ABORT sequence, ensuring ABORT can
   always be sent when needed

 - check for PCLK in the SynQuacer controller as an optional clock,
   allowing ACPI to directly provide the clock rate

 - KEBA driver Kconfig dependency fix

 - fix XIIC driver power suspend sequence

* tag 'i2c-for-6.12-rc1-additional_fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux:
  i2c: xiic: Fix pm_runtime_set_suspended() with runtime pm enabled
  i2c: keba: I2C_KEBA should depend on KEBA_CP500
  i2c: synquacer: Deal with optional PCLK correctly
  i2c: designware: fix controller is holding SCL low while ENABLE bit is disabled
2024-09-29 09:47:33 -07:00
Linus Torvalds
b81b78dacc Merge tag 'dma-mapping-6.12-2024-09-29' of git://git.infradead.org/users/hch/dma-mapping
Pull dma-mapping fix from Christoph Hellwig:

 - handle chained SGLs in the new tracing code (Christoph Hellwig)

* tag 'dma-mapping-6.12-2024-09-29' of git://git.infradead.org/users/hch/dma-mapping:
  dma-mapping: fix DMA API tracing for chained scatterlists
2024-09-29 09:35:10 -07:00
Linus Torvalds
3ed7df0852 Merge tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi
Pull more SCSI updates from James Bottomley:
 "These are mostly minor updates.

  There are two drivers (lpfc and mpi3mr) which missed the initial
  pull and a core change to retry a start/stop unit which affect
  suspend/resume"

* tag 'scsi-misc' of git://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi: (32 commits)
  scsi: lpfc: Update lpfc version to 14.4.0.5
  scsi: lpfc: Support loopback tests with VMID enabled
  scsi: lpfc: Revise TRACE_EVENT log flag severities from KERN_ERR to KERN_WARNING
  scsi: lpfc: Ensure DA_ID handling completion before deleting an NPIV instance
  scsi: lpfc: Fix kref imbalance on fabric ndlps from dev_loss_tmo handler
  scsi: lpfc: Restrict support for 32 byte CDBs to specific HBAs
  scsi: lpfc: Update phba link state conditional before sending CMF_SYNC_WQE
  scsi: lpfc: Add ELS_RSP cmd to the list of WQEs to flush in lpfc_els_flush_cmd()
  scsi: mpi3mr: Update driver version to 8.12.0.0.50
  scsi: mpi3mr: Improve wait logic while controller transitions to READY state
  scsi: mpi3mr: Update MPI Headers to revision 34
  scsi: mpi3mr: Use firmware-provided timestamp update interval
  scsi: mpi3mr: Enhance the Enable Controller retry logic
  scsi: sd: Fix off-by-one error in sd_read_block_characteristics()
  scsi: pm8001: Do not overwrite PCI queue mapping
  scsi: scsi_debug: Remove a useless memset()
  scsi: pmcraid: Convert comma to semicolon
  scsi: sd: Retry START STOP UNIT commands
  scsi: mpi3mr: A performance fix
  scsi: ufs: qcom: Update MODE_MAX cfg_bw value
  ...
2024-09-29 09:22:34 -07:00