Memory controller drivers for v6.8
Few improvements for Tegra Memory Controller: Override the SID
programming in the device, if firmware or bootloader left it in bypass
mode, e.g. after resuming from suspend. Skip prorgamming the SID, if
given Memory Controller client does not support it.
* tag 'memory-controller-drv-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
memory: tegra: Protect SID override call under CONFIG_IOMMU_API
memory: tegra: Skip SID programming if SID registers aren't set
memory: tegra: Add SID override programming for MC clients
Link: https://lore.kernel.org/r/20231213061523.4803-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
RISC-V cache drivers for v6.8
The SiFive composable cache driver moves to the cache driver
subdirectory from the drivers/soc and grows support for non-coherent
cache operations. The immediate user for these is the jh7100 SoC, that
a rake of people have on VisionFive v1 or Beagle-V Starlight boards.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-cache-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: errata: Make ERRATA_STARFIVE_JH7100 depend on !DMA_DIRECT_REMAP
riscv: errata: Add StarFive JH7100 errata
soc: sifive: ccache: Add StarFive JH7100 support
dt-bindings: cache: sifive,ccache0: Add StarFive JH7100 compatible
soc: sifive: shunt ccache driver to drivers/cache
Link: https://lore.kernel.org/r/20231221-catatonic-monday-d4c61283b136@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
RISC-V SoC drivers for v6.8
There's only one set of changes here, the addition of "Auto Update"
support for PolarFire SoC. Auto Update is one of the ways that the FPGA
bitstream can be updated, and the only one suitable for use from Linux
as it does not immediately initiate a reboot when started.
The driver was not accepted in the FPGA manager subsystem as the update
only occurs after a reboot and makes no use of the FPGA manager
framework.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
* tag 'riscv-soc-drivers-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
MAINTAINERS: add auto-update driver to mpfs entry
firmware: microchip: Replace of_device.h with explicit include
firmware: microchip: add PolarFire SoC Auto Update support
soc: microchip: mpfs: add auto-update subdev to system controller
soc: microchip: mpfs: print service status in warning message
soc: microchip: mpfs: enable access to the system controller's flash
dt-bindings: soc: microchip: add a property for system controller flash
firmware_loader: Expand Firmware upload error codes with firmware invalid error
Link: https://lore.kernel.org/r/20231221-droop-unblock-81e4fe14acee@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
mvebu drivers for 6.8 (part 1)
moxtet bus fixes
* tag 'mvebu-drivers-6.8-1' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
bus: moxtet: Add spi device table
bus: moxtet: Mark the irq as shared
Link: https://lore.kernel.org/r/87il4sbym0.fsf@BL-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Samsung SoC driver changes for v6.8
1. Add support for Google GS101 SoC to different drivers: clock
controller, serial and watchdog.
The clock driver changes depend on few bindings headers, which I put
in a topic branch with the bindings refactoring and GS101 support,
therefore this this pull request includes that bindings topic branch.
The rest of the bindings topic branch is not necessary here, however
keeping everything together makes it easier to share between
branches. The bindings topic branch is mostly refactoring all the
compatibles to add SoC-specific compatible followed by fallback.
2. Exynos ChipID: recognize ExynosAutov920.
* tag 'samsung-drivers-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: (40 commits)
dt-bindings: clock: google,gs101: rename CMU_TOP gate defines
watchdog: s3c2410_wdt: Add support for Google gs101 SoC
watchdog: s3c2410_wdt: Update QUIRK macros to use BIT macro
watchdog: s3c2410_wdt: Add support for WTCON register DBGACK_MASK bit
tty: serial: samsung: Add gs101 compatible and common fifoszdt_serial_drv_data
clk: samsung: clk-gs101: Add cmu_top, cmu_misc and cmu_apm support
clk: samsung: clk-pll: Add support for pll_{0516,0517,518}
dt-bindings: clock: google,gs101: fix incorrect numbering and DGB suffix
dt-bindings: soc: samsung: usi: add google,gs101-usi compatible
dt-bindings: serial: samsung: Make samsung,uart-fifosize a required property
dt-bindings: serial: samsung: Add google-gs101-uart compatible
dt-bindings: watchdog: Document Google gs101 watchdog bindings
dt-bindings: samsung: exynos-sysreg: combine exynosautov920 with other enum
dt-bindings: soc: google: exynos-sysreg: add dedicated SYSREG compatibles to GS101
dt-bindings: clock: Add Google gs101 clock management unit bindings
dt-bindings: soc: samsung: exynos-pmu: Add gs101 compatible
dt-bindings: watchdog: samsung: add specific compatible for Tesla FSD
dt-bindings: samsung: exynos-pmu: add specific compatible for Tesla FSD
dt-bindings: serial: samsung: add specific compatible for Tesla FSD
dt-bindings: pwm: samsung: add specific compatible for Tesla FSD
...
Link: https://lore.kernel.org/r/20231220084722.22149-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Qualcomm driver updates for v6.8
Support for SM8650 and X1E is added to the LLCC driver, the
LLCC_TRP_ATTR2_CFGn register stride is corrected, and a bug where for
each iteration looping over slices previous settings for dis_cap_alloc
and retain_on_pc are overwritten.
A quirk is introduced in UCSI, for implementations that does not handle
UCSI_GET_PDOS for non-PD partners. With this, USCI support is enabled by
default in pmic_glink. It is later reverted for SC8280XP due reported
errors.
A few memory leaks in error paths of qseecom are taken care of.
A small driver to expose the ADSP PDCharger ULOG debug log is
introduced, to aid debugging issues with pmic_glink.
The identiy of SM8650, PM8937 and a few DSPs are added to the Qualcomm
socinfo driver.
The Qualcomm sleep stats driver is extended to allow getting detailed
statistics about usage of various DDR states. Unfortunately this ABI
does not seem to be stable across platforms, so this addition is dropped
again while the reported problems are investigated further.
Andy is moved from MAINTAINERS to CREDITS. Thank you, Andy.
* tag 'qcom-drivers-for-6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (34 commits)
soc: qcom: llcc: Fix LLCC_TRP_ATTR2_CFGn offset
firmware: qcom: qseecom: fix memory leaks in error paths
soc: qcom: llcc: Fix typo in kernel-doc
dt-bindings: soc: qcom,aoss-qmp: document the X1E80100 Always-On Subsystem side channel
MAINTAINERS: qcom: move Andy Gross to credits
soc: qcom: pmic_glink: drop stray semicolons
soc: qcom: pmic_glink: disable UCSI on sc8280xp
soc: qcom: llcc: Fix dis_cap_alloc and retain_on_pc configuration
soc: qcom: pmic_pdcharger_ulog: Fix hypothetical ulog request message endianess
soc: qcom: pmic_pdcharger_ulog: Move TRACE_SYSTEM out of #if protection
soc: qcom: pmic_pdcharger_ulog: Search current directory for headers
soc: qcom: socinfo: Add few DSPs to get their image details
soc: qcom: llcc: Add missing description for members in slice config
Revert "soc: qcom: stats: Add DDR sleep stats"
dt-bindings: firmware: qcom,scm: Allow interconnect for everyone
dt-bindings: firmware: qcom,scm: document SCM on X1E80100 SoCs
soc: qcom: socinfo: Add PM8937 Power IC
soc: qcom: llcc: Add configuration data for X1E80100
dt-bindings: cache: qcom,llcc: Add X1E80100 compatible
soc: qcom: pmic_glink_altmode: fix port sanity check
...
Link: https://lore.kernel.org/r/20231219041855.732578-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
i.MX drivers change for 6.8:
- Change imx-weim bus driver to use device_get_match_data()
* tag 'imx-drivers-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
bus: imx-weim: Use device_get_match_data()
Link: https://lore.kernel.org/r/20231216064605.876196-1-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Renesas driver updates for v6.8
- Remove duplicate setup of soc_device_attribute.family,
- Make RZ/Five depend on !DMA_DIRECT_REMAP.
* tag 'renesas-drivers-for-v6.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
soc: renesas: Make RZ/Five depend on !DMA_DIRECT_REMAP
soc: renesas: Remove duplicate setup of soc_device_attribute.family
Link: https://lore.kernel.org/r/cover.1702642340.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
MediaTek soc driver updates for v6.8
This adds a refactoring of the MediaTek Smart Voltage Scaling (SVS)
driver and the addition of support for MT8186 and MT8195 in it, and
adds support for the MT8188 VDOSYS and resets in the MMSYS driver.
* tag 'mtk-soc-for-v6.8' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux: (24 commits)
soc: mediatek: mtk-svs: Constify runtime-immutable members of svs_bank
soc: mediatek: mtk-svs: Use ULONG_MAX to compare floor frequency
soc: mediatek: mtk-svs: Check if SVS mode is available in the beginning
soc: mediatek: mtk-svs: Cleanup of svs_probe() function
soc: mediatek: mtk-svs: Compress of_device_id entries
soc: mediatek: mtk-svs: Remove redundant print in svs_get_efuse_data
soc: mediatek: mtk-svs: Commonize MT8192 probe function for MT8186
soc: mediatek: mtk-svs: Drop supplementary svs per-bank pointer
soc: mediatek: mtk-svs: Commonize efuse parse function for most SoCs
soc: mediatek: mtk-svs: Move t-calibration-data retrieval to svs_probe()
soc: mediatek: mtk-svs: Add SVS-Thermal coefficient to SoC platform data
soc: mediatek: mtk-svs: Add a map to retrieve fused values
soc: mediatek: mtk-svs: Change the thermal sensor device name
soc: mediatek: mtk-svs: Reduce memory footprint of struct svs_bank
soc: mediatek: mtk-svs: Build bank name string dynamically
soc: mediatek: mtk-svs: Convert sw_id and type to enumerations
soc: mediatek: mtk-svs: Subtract offset from regs_v2 to avoid conflict
soc: mediatek: Add MT8188 VDOSYS reset bit map
soc: mediatek: Support reset bit mapping in mmsys driver
soc: mediatek: Support MT8188 VDOSYS1 Padding in mtk-mmsys
...
Link: https://lore.kernel.org/r/20231212114515.121695-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
PowerQUICC QMC and TSA drivers updates for v6.8
This pull request contains updates to prepare the support for the QMC
HDLC driver.
- Perform some fixes
- Add support for child devices
- Add QMC dynamic timeslot support
Signed-off-by: Herve Codina <herve.codina@bootlin.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
OP-TEE kernel private shared memory optimizations
Optimize OP-TEE driver private shared memory allocated as dynamic shared
memory. Both to handle larger than one page allocations and for more
efficient memory usage.
* tag 'kern-priv-shm-for-v6.8' of https://git.linaro.org/people/jens.wiklander/linux-tee:
optee: allocate shared memory with alloc_pages_exact()
optee: add page list to kernel private shared memory
Link: https://lore.kernel.org/r/20231211115815.GA616539@rayden
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
OP-TEE: asynchronous notifications with FF-A
Add support for asynchronous notifications in the OP-TEE FF-A driver. This
is the FF-A counterpart to the asynchronous notifications already
available in the OP-TEE SMC ABI.
* tag 'ffa-notif-for-v6.8' of https://git.linaro.org/people/jens.wiklander/linux-tee:
optee: ffa_abi: add asynchronous notifications
optee: provide optee_do_bottom_half() as a common function
Link: https://lore.kernel.org/r/20231211105249.GA587253@rayden
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
OP-TEE add reserved system thread
Add support for a reserved system thread in the SMC-ABI of the OP-TEE driver.
SCMI with OP-TEE transport uses this to guarantee that it will always have
a thread available in the secure world.
* tag 'system-thread-for-v6.8' of https://git.linaro.org/people/jens.wiklander/linux-tee:
firmware: arm_scmi: optee: use optee system invocation
tee: optee: support tracking system threads
tee: system session
tee: optee: system thread call property
Link: https://lore.kernel.org/r/20231211102600.GA571787@rayden
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
HiSilicon driver updates for v6.8
- Add support for the platform with PCC type3 and interrupt ack
- Few cleanups and improvements: correct the format of some strings and domain typo,
add failure log
* tag 'hisi-drivers-for-6.8' of https://github.com/hisilicon/linux-hisi:
soc: hisilicon: kunpeng_hccs: Support the platform with PCC type3 and interrupt ack
doc: kunpeng_hccs: Fix incorrect email domain name
soc: hisilicon: kunpeng_hccs: Remove an unused blank line
soc: hisilicon: kunpeng_hccs: Add failure log for no _CRS method
soc: hisilicon: kunpeng_hccs: Fix some incorrect format strings
Link: https://lore.kernel.org/r/6572C41B.6050703@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The gs101 clock defines from the bindings header are derived from the
clock register names found in the datasheet under some certain rules.
The CMU TOP gate clock defines missed to include the required "CMU"
differentiator which will cause collisions with the gate clock defines
of other clock units. Rename the TOP gate clock defines to include "CMU".
Update the clock driver to use the new defines in order to not break
compilation and bisect-ability. There are no device trees that use the
previous defines.
Fixes: 0a910f1606 ("dt-bindings: clock: Add Google gs101 clock management unit bindings")
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20231218064333.479885-1-tudor.ambarus@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Commit c14e64b469 ("soc: qcom: llcc: Support chipsets that can
write to llcc") add the support for chipset where capacity based
allocation and retention through power collapse can be programmed
based on content of SCT table mentioned in the llcc driver where
the target like sdm845 where the entire programming related to it
is controlled in firmware. However, the commit introduces a bug
where capacity/retention register get overwritten each time it
gets programmed for each slice and that results in misconfiguration
of the register based on SCT table and that is not expected
behaviour instead it should be read modify write to retain the
configuration of other slices.
This issue is totally caught from code review and programming test
and not through any power/perf numbers so, it is not known what
impact this could make if we don't have this change however,
this feature are for these targets and they should have been
programmed accordingly as per their configuration mentioned in
SCT table like others bits information.
This change brings one difference where it keeps capacity/retention
bits of the slices that are not mentioned in SCT table in unknown
state where as earlier it was initialized to zero.
Fixes: c14e64b469 ("soc: qcom: llcc: Support chipsets that can write to llcc")
Signed-off-by: Atul Dhudase <quic_adhudase@quicinc.com>
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/1701876771-10695-1-git-send-email-quic_mojha@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Sparse reports the following:
% ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- make C=2 W=1 drivers/soc/qcom/pmic_pdcharger_ulog.o
...
CC drivers/soc/qcom/pmic_pdcharger_ulog.o
CHECK drivers/soc/qcom/pmic_pdcharger_ulog.c
drivers/soc/qcom/pmic_pdcharger_ulog.c:57:34: warning: incorrect type in initializer (different base types)
drivers/soc/qcom/pmic_pdcharger_ulog.c:57:34: expected restricted __le32 [usertype] owner
drivers/soc/qcom/pmic_pdcharger_ulog.c:57:34: got int
drivers/soc/qcom/pmic_pdcharger_ulog.c:58:33: warning: incorrect type in initializer (different base types)
drivers/soc/qcom/pmic_pdcharger_ulog.c:58:33: expected restricted __le32 [usertype] type
drivers/soc/qcom/pmic_pdcharger_ulog.c:58:33: got int
drivers/soc/qcom/pmic_pdcharger_ulog.c:59:35: warning: incorrect type in initializer (different base types)
drivers/soc/qcom/pmic_pdcharger_ulog.c:59:35: expected restricted __le32 [usertype] opcode
drivers/soc/qcom/pmic_pdcharger_ulog.c:59:35: got int
Let's deal with endianness conversion in the rare case this ever runs
on a big-endian machine (and to quiet down sparse for this file).
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202312060355.M0eJtq4X-lkp@intel.com/
Fixes: 086fdb48bc ("soc: qcom: add ADSP PDCharger ULOG driver")
Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231205-pmicpdcharger-ulog-fixups-v1-3-71c95162cb84@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
As specified in samples/trace_events/Makefile:
If you include a trace header outside of include/trace/events
then the file that does the #define CREATE_TRACE_POINTS must
have that tracer file in its main search path. This is because
define_trace.h will include it, and must be able to find it from
the include/trace directory.
Without this the following compilation error is seen:
CC drivers/soc/qcom/pmic_pdcharger_ulog.o
In file included from drivers/soc/qcom/pmic_pdcharger_ulog.h:36,
from drivers/soc/qcom/pmic_pdcharger_ulog.c:15:
./include/trace/define_trace.h:95:42: fatal error: ./pmic_pdcharger_ulog.h: No such file or directory
95 | #include TRACE_INCLUDE(TRACE_INCLUDE_FILE)
| ^
compilation terminated.
Fixes: 086fdb48bc ("soc: qcom: add ADSP PDCharger ULOG driver")
Signed-off-by: Andrew Halaney <ahalaney@redhat.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20231205-pmicpdcharger-ulog-fixups-v1-1-71c95162cb84@redhat.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
The Turris Mox shares the moxtet IRQ with various devices on the board,
so mark the IRQ as shared in the driver as well.
Without this loading the module will fail with:
genirq: Flags mismatch irq 40. 00002002 (moxtet) vs. 00002080 (mcp7940x)
Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
Cc: <stable@vger.kernel.org> # v6.2+
Reviewed-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Randy reported yet another build issue with randconfigs on rv32:
WARNING: unmet direct dependencies detected for DMA_GLOBAL_POOL
Depends on [n]: !ARCH_HAS_DMA_SET_UNCACHED [=n] && !DMA_DIRECT_REMAP [=y]
Selected by [y]:
- ARCH_R9A07G043 [=y] && SOC_RENESAS [=y] && RISCV [=y] && NONPORTABLE [=y] && RISCV_ALTERNATIVE [=y] && !RISCV_ISA_ZICBOM [=n] && RISCV_SBI [=y]
This happens when DMA_DIRECT_REMAP is selected by the T-Head CMO erratum
option and DMA_GLOBAL_POOL is selected by the Andes CMO erratum. Block
selecting the RZ/Five config option, and by extension DMA_GLOBAL_POOL,
if DMA_DIRECT_REMAP has already been enabled.
Reported-by: Randy Dunlap <rdunlap@infradead.org>
Closes: https://lore.kernel.org/all/24942b4d-d16a-463f-b39a-f9dfcb89d742@infradead.org/
Tested-by: Randy Dunlap <rdunlap@infradead.org> # build-tested
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231211-primate-arbitrate-fbcd307a0b00@spud
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
These plls are found in the Tensor gs101 SoC found in the Pixel 6.
pll0516x: Integer PLL with high frequency
pll0517x: Integer PLL with middle frequency
pll0518x: Integer PLL with low frequency
PLL0516x
FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV)
PLL0517x and PLL0518x
FOUT = (MDIV * FIN)/PDIV*2^SDIV)
The PLLs are similar enough to pll_0822x that the same code can handle
both. The main difference is the change in the fout formula for the
high frequency 0516 pll.
Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor.
MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x.
When defining the PLL the "con" parameter should be set to CON3
register, like this
PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
NULL),
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Tested-by: Will McVicker <willmcvicker@google.com>
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20231211162331.435900-8-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Samsung Devicetree bindings topic branch for v6.8
Topic branch collecting several changes to Samsung SoC Devicetree
bindings:
1. Add specific compatibles to all Samsung Exynos and Tesla FSD blocks,
because that's what guidelines expect [1] and is generally
recommended practice. Existing compatibles are left untouched, thus
no driver changes are needed. The work only cleans things up, so any
future contributions will use recommended style: specific and
fallback compatibles.
2. Add bindings for new devices: Samsung ExynosAutov920 and Google
GS101.
These bindings are needed for both DTS and drivers, e.g. clock drivers.
Specifying samsung,uart-fifosize in both DT and driver static data is error
prone and relies on driver probe order and dt aliases to be correct.
Additionally on many Exynos platforms these are (USI) universal serial
interfaces which can be uart, spi or i2c, so it can change per board.
For google,gs101-uart make samsung,uart-fifosize a required property.
For this platform fifosize now *only* comes from DT.
Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20231211162331.435900-5-peter.griffin@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
