Allwinner H3 and H5 DT additions for 4.20
This is our usual H3/H5 pull request
The most notable changes are:
- the video decoding / encoding unit is finally enabled on the H3
- Mali support for the H5
- New boards: BananaPi M2+ v1.2, Orange Pi Zero Plus 2 H3 support
* tag 'sunxi-h3-h5-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
ARM: dts: sunxi: h3-h5: Add Bananapi M2+ v1.2 device trees
ARM: dts: sun8i-h3: Add Video Engine and reserved memory nodes
arm64: dts: allwinner: h5: Add device tree for Bananapi M2 Plus H5
ARM: dts: sun8i: h3: Split out non-SoC-specific parts of Bananapi M2 Plus
ARM: dts: sun8i: h3: bpi-m2-plus: Fix address for external RGMII Ethernet PHY
ARM: dts: sun8i: h3-h5: ir register size should be the whole memory block
arm64: dts: allwinner: h5: Add device node for Mali-450 GPU
ARM: dts: sun8i: Add initial Orangepi Zero Plus 2 H3 support
nvmem: sunxi-sid: add support for H5's SID controller
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Bananapi released an updated revision of the H3/H5 based Bananapi M2+.
Version 1.2 enables voltage control for the CPU's regulator by using
a GPIO line to toggle a MOSFET that can change the effective resistance
value in the regulator's feedback network.
This patch adds a common .dtsi file for this new revision, which
includes the original common sunxi-bananapi-m2-plus.dtsi file, and
adds the GPIO-controlled regulator and a cpu-supply reference. H3
and H5 variant dts files are added as well.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The Bananapi M2 Plus H5 is a variant of the original Bananapi M2 Plus,
with the H3 SoC replaced with an H5. Everything else is the same.
Add a stub device tree incorporating the shared bananapi-m2-plus dtsi
file.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Three more variants of the Bananapi M2 Plus have been introduced. One
with the H5 instead of the H3, another with the H2+ instead, and the
last with the H3 but with WiFi and eMMC removed.
All these variants use the same board. This patch splits out the
non-SoC-specific parts of the device tree, so that they can be shared
among all the variants. The original Bananapi M2 Plus has been renamed
to Bananapi M2 Plus H3.
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The external RTL8211E RGMII Ethernet PHY is configured via external
resistors to use the address 0x1. The 0x0 address is a broadcast address
for this family of PHYs, and should not be used explicitly.
Fixes: 8c7ba536e7 ("ARM: sun8i: bananapi-m2-plus: Enable dwmac-sun8i")
Fixes: 4904337fe3 ("ARM: dts: sunxi: Restore EMAC changes (boards)")
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The size of the register should be the size of the whole memory block,
not just the registers, that are needed.
Signed-off-by: Philipp Rossak <embed3d@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
The H5 has a Mali-450 GPU with 4 Pixel Processor cores.
Interestingly, while the datasheet lists an interrupt line for the GPU's
PMU, the hardware block itself doesn't seem to have it. Reads from the
PMU address range all return zero, and writes are ignored.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Orangepi Zero Plus 2 is an open-source single-board computer, available in two
Allwinner SOC variants, H3 and H5. We add support for H3 variant here, as the
H5 is already supported by sun50i-h5-orangepi-zero-plus2.dts.
H3 Orangepi Zero Plus 2 has:
- Quad-core Cortex-A7
- 512MB DDR3
- microSD slot and 8GB eMMC
- Debug TTL UART
- HDMI
- Wifi + BT
- OTG + power supply
Signed-off-by: Diego Rondini <diego.rondini@kynetics.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
The H5 SoC have a SID controller that looks like the one in A64, the
cells are in the same offset but doesn't contain the same data (thermal
sensor calibration for example).
Add a binding for it.
Signed-off-by: Emmanuel Vadot <manu@freebsd.org>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Second Round of Renesas ARM Based SoC DT Updates for v4.20
* RZ/G1M (r8a7743) based iWave G20D-Q7 board and camera daughter board
- Move PCIe node out of common dtsi to allow reuse of the common dtsi
on the iWave RZ/G1N board
* RZ/G1C (r8a77470) SoC: Add I2C4, SDHI2 and SMP support
* R-Car Gen1 based boards and R-Car Gen2 SoCs:
- Enhance top-of-file comments to include SoC name
* RZ/N1D (r9a06g032) SoC:
- Correct UART0 description and add all other UARTs
* tag 'renesas-arm-dt2-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: dts: iwg20d-q7-common: Move pciec node out of common dtsi
ARM: dts: r8a77470: Add I2C4 support
ARM: dts: r8a77470: Add SDHI2 support
ARM: dts: r8a77470: Add SMP support
ARM: dts: R-Car Gen1 board comment update
ARM: dts: Include R-Car Gen2 product name in DTSI files
ARM: dts: r9a06g032: Correct UART and add all other UARTs
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
arm64: tegra: Device tree changes for v4.20-rc1
This contains mostly device tree changes to support faster SDHCI modes
on Tegra210 and Tegra186.
* tag 'tegra-for-4.20-arm64-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
arm64: tegra: I2C on Tegra194 is not compatible with Tegra114
arm64: dts: tegra186: Enable HS400
arm64: dts: tegra210: Enable HS400
arm64: dts: tegra186: Add SDMMC4 DQS trim value
arm64: dts: tegra210: Add SDMMC4 DQS trim value
arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4
arm64: dts: tegra210: Assign clocks for sdmmc1 and sdmmc4
arm64: dts: tegra186: Add SDHCI tap and trim values
arm64: dts: tegra210: Add SDHCI tap and trim values
arm64: dts: tegra186: Add sdmmc pad auto calibration offsets
arm64: dts: tegra210: Add sdmmc pad auto calibration offsets
arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1
arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply
arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V
arm64: dts: Add Tegra186 sdmmc pinctrl voltage states
arm64: dts: Add Tegra210 sdmmc pinctrl voltage states
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
dt-bindings: Changes for v4.20-rc1
This contains the PMC pad configuration bindings which are used to
control the voltage of various pads found on Tegra chips. Among other
things this is required to enable faster modes on SDHCI.
* tag 'tegra-for-4.20-dt-bindings' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
dt-bindings: Add Tegra PMC pad configuration bindings
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This device-tree pxa update brings :
- a couple of changes for future pxa2xx platforms
- 2 fixes in RTC and I2C domain
* tag 'pxa-dt-4.20' of https://github.com/rjarzmik/linux:
ARM: dts: pxa: add pincontrol helpers
ARM: dts: pxa: fix power i2c base address
ARM: dts: pxa: fix the rtc controller
ARM: dts: pxa: change serial node names
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Amlogic ARM64 DT updates for v4.20, round 2
- new SoC support: basic support for G12A family
- new board: Amlogic U200 board, using G12A SoC
- fix SPI bus warnings from new dtc updates
* tag 'amlogic-dt64-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT support
dt-bindings: arm: amlogic: Add Meson G12A binding
arm64: dts: meson: Fix erroneous SPI bus warnings
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
ARM: dts: Amlogic updates for v4.20
- fix clock controller register sizes
- new board: Endless Mini (EC-100) by Endless Mobile
- add voltage regulators
* tag 'amlogic-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
ARM: dts: meson8b: odroidc1: add stdout-path property
ARM: dts: meson8b: odroidc1: enable the SAR ADC
ARM: dts: meson8b: odroidc1: add the fixed voltage regulators
ARM: dts: meson8b: odroidc1: add the CPU voltage regulator
ARM: dts: meson8b: Add support for the Endless Mini (EC-100)
ARM: dts: meson8b: add the RMII pins
ARM: dts: meson8b: add the I2C_A, PWM_C and UART_B pins
dt-bindings: arm: amlogic: Add the Endless Mobile Endless Mini (EC-100)
dt-bindings: add vendor prefix for "Endless Mobile, Inc."
ARM: dts: meson8b: fix the clock controller register size
ARM: dts: meson8: fix the clock controller register size
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Berlin64 DT changes for v4.20
* tag 'berlin64-dt-for-v4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/jszhang/linux-berlin:
arm64: dts: synaptics: add dtsi file for Synaptics AS370 SoC
dt-bindings: arm: syna: add support for the AS370 SoC
dt-bindings: arm: move berlin binding documentation to syna.txt
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
SPI controller nodes should be named 'spi' rather than 'ssp'. Fixing the
name enables dtc SPI bus checks.
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
SPI controller nodes should be named 'spi' rather than 'ssp'. Fixing the
name enables dtc SPI bus checks.
Cc: Chanho Min <chanho.min@lge.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
dtc has new checks for SPI buses. Fix the warnings in node names.
arch/arm64/boot/dts/amd/amd-overdrive.dtb: Warning (spi_bus_bridge): /smb/ssp@e1030000: node name for SPI buses should be 'spi'
arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dtb: Warning (spi_bus_bridge): /smb/ssp@e1030000: node name for SPI buses should be 'spi'
arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dtb: Warning (spi_bus_bridge): /smb/ssp@e1030000: node name for SPI buses should be 'spi'
Cc: Brijesh Singh <brijeshkumar.singh@amd.com>
Cc: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
PCIe is not populated by default on iWave RZ/G1N board. RZ/G1N board
is almost identical to RZ/G1M. In order to reuse the common dtsi for
both the boards, it is required to move pcie node from common dtsi
to board specific dts.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Include R-Car Gen1 product names for Bock-W and Marzen.
The product names are taken from:
Documentation/devicetree/bindings/arm/shmobile.txt
Signed-off-by: Magnus Damm <damm@opensource.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Improve the user friendliness of the DTS code base by including the
R-Car product name in each R-Car Gen2 DTSI file.
The product names are taken from:
Documentation/devicetree/bindings/arm/shmobile.txt
Signed-off-by: Magnus Damm <damm@opensource.se>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The AS370 SoC is a new derivative of the berlin family. However, the
SoC isn't named as berlin*.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Move berlin binding documentation as part of transition from Marvell
berlin to Synaptics SoC.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: Rob Herring <robh@kernel.org>
The power key is controlled solely by the EC, which only tiggeres this
gpio after wakeup.
Fixes immediately return to suspend after wake from LP1.
Signed-off-by: Marc Dietrich <marvin24@gmx.de>
Tested-by: Nicolas Chauvet <kwizart@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Fix indentation and alignment when spaces were used instead of tabs.
This fixes checkpatch errors like:
ERROR: code indent should use tabs where possible
#306: FILE: arch/arm/boot/dts/tegra20-paz00.dts:306:
+^I^I <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;$
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add an evaluation board device tree more in-line with all our other
device trees.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Rename ac97 label to tegra_ac97 to be more in-line with the device tree
binding documentation.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Get rid of the fake clocks simple bus and use node names as per the
actual schematics.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Rename i2c_ddc to hdmi_ddc to be more in-line with other device trees.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Drop model and compatible nodes from the module level device tree as
they get overridden by the carrier board device tree anyway.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Simplify model and compatible by dropping the 256/512 MB from the model,
-512 from the compatible and rename that property from toradex,iris to
toradex,colibri_t20-iris to be more in-line with all our other device
trees.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Simplify model and compatible by dropping the 256/512 MB from the model
and -512 from the compatible properties to be more in-line with all our
other device trees.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Annotate the SD card, its detect pin and move the SD card detect GPIO
definition from the module to the carrier board more in-line with our
other device trees.
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
