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Samuel Holland
88df36f2e6 pinctrl: sunxi: Support the 2.5V I/O bias mode 
H616 and newer SoCs feature a 2.5V I/O bias mode in addition to the
1.8V and 3.3V modes. This mode is entered by selecting the 3.3V level
and disabling the "withstand function".

H616 supports this capability on its main PIO only. A100 supports this
capability on both its PIO and R-PIO.

Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220713025233.27248-4-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-18 11:39:33 +02:00
Samuel Holland
fc153c8f28 pinctrl: sunxi: Add I/O bias setting for H6 R-PIO 
H6 requires I/O bias configuration on both of its PIO devices.
Previously it was only done for the main PIO.

The setting for Port L is at bit 0, so the bank calculation needs to
account for the pin base. Otherwise the wrong bit is used.

Fixes: cc62383fce ("pinctrl: sunxi: Support I/O bias voltage setting on H6")
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220713025233.27248-3-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-18 11:39:33 +02:00
Samuel Holland
329d32a987 dt-bindings: pinctrl: Add compatible for Allwinner D1 
D1 contains a pin controller similar to previous SoCs, but with some
register layout changes. It includes 6 interrupt-capable pin banks.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220713025233.27248-2-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-18 11:39:33 +02:00
Robert Marko
6cd81a86ff pinctrl: qcom-pmic-gpio: add support for PMP8074 
PMP8074 has 12 GPIO-s with holes on GPIO1 and GPIO12.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Link: https://lore.kernel.org/r/20220711203408.2949888-4-robimarko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-18 11:38:37 +02:00
Robert Marko
ed16b6d774 dt-bindings: pinctrl: qcom,pmic-gpio: add PMP8074 
Document the compatible for PMP8074 which has 12 GPIO-s with holes at
GPIO1 and GPIO12.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220711203408.2949888-3-robimarko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-18 11:38:37 +02:00
Dominik Kobinski
eebe11b5bb pinctrl: qcom: spmi-gpio: Add pm8226 compatibility 
Add support for pm8226 SPMI GPIOs. The PMIC features
8 GPIOs, with no holes inbetween.

Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Suggested-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Signed-off-by: Dominik Kobinski <dominikkobinski314@gmail.com>
Link: https://lore.kernel.org/r/20211125215310.62371-1-dominikkobinski314@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-18 11:38:37 +02:00
Andy Shevchenko
03da7f9873 pinctrl: core: Use device_match_of_node() helper 
Instead of open coding, use device_match_of_node() helper.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Link: https://lore.kernel.org/r/20220629115840.16241-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-18 11:38:37 +02:00
AngeloGioacchino Del Regno
e4c04e7a17 dt-bindings: pinctrl: mt8195: Add gpio-line-names property 
Add the 'gpio-line-names' property to mt8195-pinctrl, as this will be
used in devicetrees to describe pin names.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Link: https://lore.kernel.org/r/20220630110453.186526-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-18 11:38:36 +02:00
AngeloGioacchino Del Regno
1b3ab63e56 dt-bindings: pinctrl: mt8195: Add and use drive-strength-microamp 
As was already done for MT8192 in commit b52e695324 ("dt-bindings:
pinctrl: mt8192: Add drive-strength-microamp"), replace the custom
mediatek,drive-strength-adv property with the standardized pinconf
'drive-strength-microamp' one.

Similarly to the mt8192 counterpart, there's no user of property
'mediatek,drive-strength-adv', hence removing it is safe.

Fixes: 69c3d58dc1 ("dt-bindings: pinctrl: mt8195: Add mediatek,drive-strength-adv property")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220630131543.225554-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-18 11:38:36 +02:00
AngeloGioacchino Del Regno
11bd0ffd16 dt-bindings: pinctrl: mt8195: Fix name for mediatek,rsel-resistance-in-si-unit 
When this property was introduced, it contained underscores, but
the actual code wants dashes.

Change it from mediatek,rsel_resistance_in_si_unit to
mediatek,rsel-resistance-in-si-unit.

Fixes: 91e7edceda ("dt-bindings: pinctrl: mt8195: change pull up/down description")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220630122334.216903-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-18 11:38:36 +02:00
Claudiu Beznea
04156e7dd7 pinctrl: at91: remove #ifdef CONFIG_PM 
Remove #ifdef CONFIG_PM and use pm_ptr() macro instead.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220704101253.808519-2-claudiu.beznea@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-18 11:38:36 +02:00
Claudiu Beznea
cc701e18a9 pinctrl: at91-pio4: remove #ifdef CONFIG_PM_SLEEP 
Remove #ifdef CONFIG_PM_SLEEP and use pm_sleep_ptr() macro instead.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220704101253.808519-1-claudiu.beznea@microchip.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-18 11:38:36 +02:00
Andre Przywara
c1e72763ae dt-bindings: pinctrl: sunxi: allow vcc-pi-supply 
The Allwinner H616 SoC contains a VCC_PI pin, which supplies the voltage
for GPIO port I.
Extend the range of supply port names to include vcc-pi-supply to cover
that.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220708105235.3983266-5-andre.przywara@arm.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-11 10:47:34 +02:00
Andre Przywara
ee84131b43 dt-bindings: pinctrl: sunxi: Make interrupts optional 
The R_PIO pinctrl device on the Allwinner H616 SoC does not have an
interrupt (it features only two pins).
However the binding requires at least naming one upstream interrupt,
plus the #interrupt-cells and interrupt-controller properties.

Drop the unconditional requirement for the interrupt properties, and
make them dependent on being not this particular pinctrl device.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220708105235.3983266-3-andre.przywara@arm.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-11 10:46:51 +02:00
Stephan Gerhold
4528a0cf79 pinctrl: qcom: Add pinctrl driver for MSM8909 
Make it possible to control pins using the TLMM block in the MSM8909 SoC
by adding the necessary definitions for GPIOs, groups and functions.

The driver is originally taken from the msm-4.9 release [1] from Qualcomm,
but cleaned up significantly with several fixes and clarifications.

[1]: https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LF.UM.8.7-22500-8x09.0/drivers/pinctrl/qcom/pinctrl-msm8909.c

Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220628145502.4158234-3-stephan.gerhold@kernkonzept.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-11 10:26:52 +02:00
Stephan Gerhold
c249ec7ba1 dt-bindings: pinctrl: Add DT schema for qcom,msm8909-tlmm 
Document the "qcom,msm8909-tlmm" compatible for the TLMM/pin control
block in the MSM8909 SoC, together with the allowed GPIOs and functions.

Signed-off-by: Stephan Gerhold <stephan.gerhold@kernkonzept.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220628145502.4158234-2-stephan.gerhold@kernkonzept.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-11 10:26:52 +02:00
Jianlong Huang
e2961cd685 pinctrl: starfive: Serialize adding groups and functions 
The pinctrl dt_node_to_map method may be called in parallel which leads
us to call pinconf_generic_add_group and pinconf_generic_add_function
in parallel. This is not supported though and leads to errors, so add a
mutex to serialize these calls.

Signed-off-by: Jianlong Huang <jianlong.huang@starfivetech.com>
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Link: https://lore.kernel.org/r/20220627085333.1774396-1-emil.renner.berthing@canonical.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-11 10:22:57 +02:00
Linus Walleij
04131ae29b Merge tag 'renesas-pinctrl-for-v5.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel 
pinctrl: renesas: Updates for v5.20 (take two)

  - Add support for the RZ/V2M and R-Car V4H SoCs,
  - Miscellaneous fixes and improvements.
 2022-07-10 01:10:14 +02:00
Basavaraj Natikar
6011c7e9c0 pinctrl: amd: Remove contact information 
Remove contact information.

Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
Link: https://lore.kernel.org/r/20220613064127.220416-4-Basavaraj.Natikar@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-10 01:09:21 +02:00
Basavaraj Natikar
b8c824a869 pinctrl: amd: Don't save/restore interrupt status and wake status bits 
Saving/restoring interrupt and wake status bits across suspend can
cause the suspend to fail if an IRQ is serviced across the
suspend cycle.

Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
Fixes: 79d2c8bede ("pinctrl/amd: save pin registers over suspend/resume")
Link: https://lore.kernel.org/r/20220613064127.220416-3-Basavaraj.Natikar@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-10 01:09:21 +02:00
Basavaraj Natikar
21793d228c pinctrl: amd: Use devm_platform_get_and_ioremap_resource 
Use devm_platform_get_and_ioremap_resource() to simplify code.

Signed-off-by: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
Link: https://lore.kernel.org/r/20220613064127.220416-2-Basavaraj.Natikar@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-10 01:09:21 +02:00
Linus Walleij
5495d1636b Merge tag 'intel-pinctrl-v5.20-1' of gitolite.kernel.org:pub/scm/linux/kernel/git/pinctrl/intel into devel 
intel-pinctrl for v5.20-1

* Update MAINTAINERS to set the Intel pin control status to Supported
* Switch Intel pin control drivers to use struct pingroup

The following is an automated git shortlog grouped by driver:

baytrail:
 -  Switch to to embedded struct pingroup

cherryview:
 -  Switch to to embedded struct pingroup

intel:
 -  Add Intel Meteor Lake pin controller support
 -  Drop no more used members of struct intel_pingroup
 -  Switch to to embedded struct pingroup
 -  Embed struct pingroup into struct intel_pingroup

lynxpoint:
 -  Switch to to embedded struct pingroup

MAINTAINERS:
 -  Update Intel pin control to Supported

Merge branch 'ib-v5.20-amd-pinctrl':
 - Merge branch 'ib-v5.20-amd-pinctrl'

merrifield:
 -  Switch to to embedded struct pingroup
 2022-07-10 01:07:08 +02:00
Robert Marko
7542766e78 pinctrl: qcom: spmi-gpio: make the irqchip immutable 
Commit 6c846d026d ("gpio: Don't fiddle with irqchips marked as
immutable") added a warning to indicate if the gpiolib is altering the
internals of irqchips.

Following this change the following warning is now observed for the SPMI
PMIC pinctrl driver:
gpio gpiochip1: (200f000.spmi:pmic@0:gpio@c000): not an immutable chip, please consider fixing it!

Fix this by making the irqchip in the SPMI PMIC pinctrl driver immutable.

Signed-off-by: Robert Marko <robimarko@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Tested-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20220624195112.894916-1-robimarko@gmail.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-07-10 01:04:51 +02:00
Kuninori Morimoto
36611d28f5 pinctrl: renesas: r8a779g0: Add missing MODSELx for AVBx 
AVB1 needs MODSEL6, AVB2 needs MODSEL5 settings.
This patch adds missing MODSELx settings for the affected pins.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87k08xsj81.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:37 +02:00
Kuninori Morimoto
36fb7b8af5 pinctrl: renesas: r8a779g0: Add missing MODSELx for TSN0 
TSN0 needs MODSEL4 settings.
This patch adds missing MODSELx settings for the affected pins.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87letdsj8e.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:37 +02:00
Kuninori Morimoto
b811062e5f pinctrl: renesas: r8a779g0: Add missing ERROROUTC_A 
This patch adds missing ERROROUTC_A settings.
Current existing ERROROUTC should be _B, this patch tidies it up.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87mtdtsj8m.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:37 +02:00
Kuninori Morimoto
c606c2fde2 pinctrl: renesas: r8a779g0: Add missing PWM 
R-Car V4H has PWM/PWM_A/PWM_B, but current PFC setting is mixed.
This patch adds missing PWM settings, and tidies these up.

According to Document, GP3_14 Function4 is PWM2_A,
but we can't select it at P1SR3[27:24].
This patch just ignore it for now.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87o7y9sj90.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:37 +02:00
Kuninori Morimoto
1c2646b5ce pinctrl: renesas: r8a779g0: Add missing FlexRay 
This patch adds missing FlexRay pins.
Because Document (Rev.0.51) has 2x FXR_TXENA/B pin with no suffix (_A, _B),
this patch names them as _X.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87pmipsj9a.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:37 +02:00
Kuninori Morimoto
85a9cbe4c5 pinctrl: renesas: r8a779g0: Add missing TPU0TOx_A 
This patch adds missing TPU0TOx_A.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87r135sj9j.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:37 +02:00
Kuninori Morimoto
c2b4b2cd63 pinctrl: renesas: r8a779g0: Add missing CANFD5_B 
This patch adds missing CANFD5_B.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87sfnlsj9t.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:37 +02:00
Kuninori Morimoto
9c151c2be9 pinctrl: renesas: r8a779g0: Add missing SCIF1_X 
This patch adds missing SCIF1_X.
Because Document (Rev.0.51) has 2x SCIF1 with no suffix (_A, _B),
this patch names it as _X.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87tu81sja1.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:37 +02:00
Kuninori Morimoto
49e4697656 pinctrl: renesas: r8a779g0: Add missing SCIF3 
R-Car V4H has SCIF3 and SCIF3_A, but current PFC setting is mixed.
This patch cleans up SCIF3/SCIF3_A, based on Rev.0.51.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87v8shsja7.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:37 +02:00
Kuninori Morimoto
cf4f789184 pinctrl: renesas: r8a779g0: Add missing HSCIF1_X 
This patch adds missing HSCIF1.
Because Document (Rev.0.51) has 2x HSCIF1 with no suffix (_A, _B),
this patch names it as _X.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87wncxsjah.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:37 +02:00
Kuninori Morimoto
213b713255 pinctrl: renesas: r8a779g0: Add missing HSCIF3_A 
This patch adds missing HSCIF3_A.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87y1xdsjar.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:37 +02:00
Kuninori Morimoto
1b23d8a478 pinctrl: renesas: r8a779g0: Add missing IRQx_A/IRQx_B 
This patch adds missing IRQx_A/IRQx_B, and tidies up existing IRQs.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87zghtsjb4.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:37 +02:00
Kuninori Morimoto
0df46188a5 pinctrl: renesas: r8a779g0: Add missing TCLKx_A/TCLKx_B/TCLKx_X 
This patch adds missing TCLKx_A/TCLKx_B/TCLKx_X.

Because Document (Rev.0.51) has 2x TCLK3/TCLK4 with no suffix (_A, _B),
this patch names them as _X.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/871qv5txvt.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:37 +02:00
Kuninori Morimoto
475425ee38 pinctrl: renesas: r8a779g0: Tidyup POC1 voltage 
According to Rev.0.51 datasheet 004_R-CarV4H_pin_function.xlsx,
GP1_23 - GP1_28 are 1.8/3.3V.  But they are not on Table 7.28.
According to the HW team, there are no bits assigned.
This patch follows HW team's comment.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/8735fltxwg.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:37 +02:00
Kuninori Morimoto
5a494f02b8 pinctrl: renesas: r8a779g0: Tidy up ioctrl_regs 
Remove POC2 which is not documented, and remove TD0SEL3 which is not
needed.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/874k01txy9.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:37 +02:00
Kuninori Morimoto
b279b54b50 pinctrl: renesas: r8a779g0: Remove unused MOD_SELx definitions 
Current R-Car V4H PFC code has many MOD_SELx definitions with all 0.
But these have no meaning.  This patch removes them.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/875ykhtxym.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:36 +02:00
Kuninori Morimoto
1204bc463b pinctrl: renesas: r8a779g0: Remove unused IPxSRx definitions 
Current R-Car V4H PFC code has many IPxSRx definitions with all 0.
But these have no meaning.  This patch removes them.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/877d4xtxyv.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:36 +02:00
Kuninori Morimoto
aa83be7c8d pinctrl: renesas: r8a779g0: Remove unused NOGP definitions 
Current R-Car V4H PFC code has many NOGP definitions.  But these are not
used, and they are different from original usage.  This patch removes
them.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/878rpdtxz8.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:36 +02:00
Kuninori Morimoto
42cbd16e7c pinctrl: renesas: r8a779g0: Fixup MODSEL8 
MODSEL8 controls I2C vs. GPIO modes, and the Datasheet (Rev.0.51) is
indicating that I2C needs 1.  But we should use 0 for all cases in
reality.  New Datasheet should be updated.

Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87a69ttxzg.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:36 +02:00
Phong Hoang
050442ae4c pinctrl: renesas: r8a779g0: Add pins, groups and functions 
This patch adds SCIF, I2C, EthernetAVB, HSCIF, MMC, QSPI, MSIOF, PWM,
CAN-FD, Ethernet-TSN, PCIe pins, groups, and functions.

This patch was created based on the Rev.0.51 datasheet.

Signed-off-by: Phong Hoang <phong.hoang.wz@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com>
Signed-off-by: CongDang <cong.dang.xn@renesas.com>
Signed-off-by: Kazuya Mizuguch <kazuya.mizuguchi.ks@renesas.com>
Signed-off-by: Tho Vu <tho.vu.wh@renesas.com>
[Morimoto: merged above patches into one, cleanup white space, sort modules alphabetically, fixup comments]
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87bku9ty0b.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:36 +02:00
LUU HOAI
ad9bb2fec6 pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support 
This patch adds initial pinctrl support for the R-Car V4H (R8A779G0)
SoC, including bias, drive strength and voltage control.

This patch was created based on the Rev.0.51 datasheet.

Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
[Morimoto: merge Kihara-san's MODSEL8 fixup patch, cleanup white space, care about reserved bits on each configs, fixup comments, etc.]
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87czepty0j.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:36 +02:00
Kuninori Morimoto
665f77eb0d pinctrl: renesas: Add PORT_GP_CFG_13 macros 
Add PORT_GP_CFG_13() and PORT_GP_13() helper macros, to be used by the
r8a779g0 subdriver.

Based on a larger patch in the BSP by LUU HOAI.

Signed-off-by: LUU HOAI <hoai.luu.ub@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87edz5ty0r.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:36 +02:00
Kuninori Morimoto
1929683e5b dt-bindings: pinctrl: renesas,pfc: Document r8a779g0 support 
Document Pin Function Controller (PFC) support for the Renesas R-Car V4H
(R8A779G0) SoC.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87fsjlty13.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:36 +02:00
Phil Edworthy
92a9b82525 pinctrl: renesas: Add RZ/V2M pin and gpio controller driver 
Add support for pin and gpio controller driver for RZ/V2M SoC.
Based on the RZ/G2L driver.

Note that the DETDO and DETMS dedicated pins are currently not
documented in the HW manual as to which pin group they are in.
HW team has since said that the output level of 1.8V I/O group 4
(for MD0-7, and debugger) is the same as the 1.8V I/O group 3.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220624084833.22605-3-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-05 09:12:36 +02:00
Phil Edworthy
34e3b69b1e dt-bindings: pinctrl: Add DT bindings for Renesas RZ/V2M pinctrl 
Add device tree binding documentation and header file for Renesas
RZ/V2M pinctrl.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220624084833.22605-2-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
 2022-07-01 09:04:40 +02:00
Andy Shevchenko
25097de7b2 pinctrl: intel: Add Intel Meteor Lake pin controller support 
This driver adds pinctrl/GPIO support for Intel Meteor Lake. The
GPIO controller is based on the next generation GPIO hardware but still
compatible with the one supported by the Intel core pinctrl/GPIO driver.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com>
 2022-06-30 17:09:18 +03:00
Samuel Holland
d4c0b614b5 pinctrl: axp209: Support the AXP221/AXP223/AXP809 variant 
These PMICs each have 2 GPIOs with the same register layout as AXP813,
but without an ADC function. They all fall back to the AXP221 compatible
string, so only that one needs to be listed in the driver.

Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Link: https://lore.kernel.org/r/20220621034224.38995-4-samuel@sholland.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
 2022-06-30 14:05:57 +02:00