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Bjorn Andersson
77cbca3a12 phy: qcom-qmp-combo: Extend phy_mutex to all phy_ops 
The phy core ensures mutual exclusion across the ops for a given phy,
but the upcoming introduction of USB Type-C orientation switching might
race with the DisplayPort phy operations. So extend the mutual exclusion
to cover the remaining ops as well, to avoid concurrent reconfiguration
of the hardware.

Reported-by: Johan Hovold <johan@kernel.org>
Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20230515032743.400170-4-quic_bjorande@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-19 23:17:19 +05:30
Bjorn Andersson
02545aa310 phy: qcom-qmp-combo: Move phy_mutex out of com_init/exit 
With the upcoming introduction of USB Type-C orientation switching the
region of mutual exclusion needs to be extended to cover both the common
init/exit as well as the individual functions.

So move the phy_mutex one step up the stack.

Reviewed-by: Johan Hovold <johan+linaro@kernel.org>
Tested-by: Abel Vesa <abel.vesa@linaro.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450
Tested-by: Johan Hovold <johan+linaro@kernel.org>	# X13s
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20230515032743.400170-3-quic_bjorande@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-19 23:17:19 +05:30
Bjorn Andersson
6c0237db15 dt-bindings: phy: qcom,sc8280xp-qmp-usb43dp: Add ports and orientation-switch 
The QMP combo phy can be connected to a TCPM, a USB controller and a
DisplayPort controller for handling USB Type-C orientation switching
and propagating HPD signals.

Extend the binding to allow these connections to be described.

Tested-by: Abel Vesa <abel.vesa@linaro.org>
Tested-by: Steev Klimaszewski <steev@kali.org>
Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on HDK8450
Tested-by: Johan Hovold <johan+linaro@kernel.org>	# X13s
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com>
Link: https://lore.kernel.org/r/20230515032743.400170-2-quic_bjorande@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-19 23:17:18 +05:30
Vinod Koul
940797d6d5 Merge branch 'fixes' into next 
This brings in the Qcom qmp patch fixes into next as well
 2023-05-19 23:16:43 +05:30
Frank Li
afa9294912 dt-bindings: phy: cdns,salvo: add property cdns,usb2-disconnect-threshold-microvolt 
Add cdns,usb2-disconnect-threshold-microvolt property to address fake USB
disconnection issue during enumeration or suspend state for difference
platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20230517161646.3418250-7-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-19 23:14:07 +05:30
Frank Li
e8c3336134 phy: cadence: salvo: Add cdns,usb2-disconnect-threshold-microvolt property 
Add cdns,usb2-disconnect-threshold-microvolt property to address fake USB
disconnection issue during enumeration or suspend state for difference
platform.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20230517161646.3418250-6-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-19 23:14:06 +05:30
Peter Chen
3ad5cebe9c phy: cadence: salvo: add .set_mode API 
For NXP platform design, the PHY can't know VBUS well, it causes the FSM
in controller seeing the disconnection at L1 use case. With .set_mode API
introduced, the controller driver could force PHY seeing B Session VALID
when it is at the device mode (VBUS is there), and keep FSM working well.

Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20230517161646.3418250-5-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-19 23:14:06 +05:30
Peter Chen
fe5516651e phy: cadence: salvo: add bist fix 
Very limited parts may fail to work on full speed mode (both host and
device modes) for USB3 port due to higher threshold in full speed receiver
of USB2.0 PHY.

One example failure symptom is, the enumeration is failed when connecting
full speed USB mouse to USB3 port, especially under high temperature.

The workaround is to configure threshold voltage value of single ended
receiver by setting USB2.0 PHY register AFE_RX_REG5[2:0] to 3'b101.

Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20230517161646.3418250-4-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-19 23:14:06 +05:30
Peter Chen
1492498d13 phy: cadence: salvo: decrease delay value to zero for txvalid 
For USB2 L1 use cases, some hosts may start transferring less than 20us
after End of Resume, it causes the host seeing corrupt packet from the
device side. The reason is the delay time between PHY powers up and
txvalid is 20us. To fix it, we change the delay value as 0us.

Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20230517161646.3418250-3-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-19 23:14:06 +05:30
Peter Chen
88bc4cda5e phy: cadence: salvo: add access for USB2PHY 
There is an offset for USB2PHY in SALVO phy, add offset parameter for read
and write API to cover both USB2 and USB3 PHY control.

Signed-off-by: Peter Chen <peter.chen@nxp.com>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20230517161646.3418250-2-Frank.Li@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-19 23:14:06 +05:30
Bhupesh Sharma
1178c93c0a phy: qcom-qmp-usb: add support for updated qcm2290 / sm6115 binding 
Add support for the new qcm2290 / sm6115 binding.

The USB QMP phy on these devices supports 2 lanes. Note that the
binding now does not describe every register subregion and instead
the driver holds the corresponding offsets.

While at it also include support for PCS_MISC region which was left
out earlier.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Link: https://lore.kernel.org/r/20230516150511.2346357-3-bhupesh.sharma@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-17 13:44:02 +05:30
Bhupesh Sharma
2daece5eb5 dt-bindings: phy: qcom,qmp-usb: Drop legacy bindings and move to newer one (SM6115 & QCM2290) 
'qcom,msm8996-qmp-usb3-phy.yaml' defines bindings for several PHYs
which predate USB -> USB+DP migration. Since SM6115 and QCM2290
nodes for USB QMP phy are being added to dtsi files by followup patches,
move these bindings instead to the newer style
'qcom,sc8280xp-qmp-usb3-uni-phy.yaml' file.

Since no device trees use these bindings presently, so we have no ABI breakages
with this patch.

Signed-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>
Link: https://lore.kernel.org/r/20230516150511.2346357-2-bhupesh.sharma@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-17 13:44:02 +05:30
Siddharth Vadapalli
8d087a09c7 phy: ti: gmii-sel: Enable USXGMII mode for J784S4 
TI's J784S4 SoC supports USXGMII mode with the CPSW9G instance's MAC
ports 1 and 2. Add USXGMII mode to the extra_modes member of J784S4's
SoC data.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230331062521.529005-3-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-16 20:01:44 +05:30
Siddharth Vadapalli
efd658807d phy: ti: gmii-sel: Add support for CPSW9G GMII SEL in J784S4 
Each of the CPSW9G ports in TI's J784S4 SoC support modes such as QSGMII.

Add a new compatible for it and allow the usage of "ti,qsgmii-main-ports"
property for J784S4.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230331062521.529005-2-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-16 20:01:43 +05:30
Siddharth Vadapalli
2de2e49b32 phy: ti: gmii-sel: Enable SGMII mode for J721E 
TI's J721E SoC supports SGMII mode with the CPSW9G instance of the CPSW
Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the
corresponding extra_modes member.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230309063514.398705-4-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-16 20:00:52 +05:30
Siddharth Vadapalli
178b651521 phy: ti: gmii-sel: Enable SGMII mode for J7200 
TI's J7200 SoC supports SGMII mode with the CPSW5G instance of the CPSW
Ethernet Switch. Thus, enable it by adding SGMII mode to the list of the
corresponding extra_modes member.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230309063514.398705-3-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-16 20:00:52 +05:30
Siddharth Vadapalli
6a30118842 phy: ti: gmii-sel: Add support for SGMII mode 
Add support to configure the CPSW MAC's PHY in SGMII mode if the SoC
supports it. The extra_modes member of the phy_gmii_sel_soc_data struct
corresponding to the SoC is used to determine whether or not the SoC
supports SGMII mode.

Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Reviewed-by: Roger Quadros <rogerq@kernel.org>
Link: https://lore.kernel.org/r/20230309063514.398705-2-s-vadapalli@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-16 20:00:51 +05:30
Yang Li
1541fbaca0 phy: freescale: imx8m-pcie: Use devm_platform_ioremap_resource() 
Convert platform_get_resource(),devm_ioremap_resource() to a single
call to devm_platform_ioremap_resource(), as this is exactly what this
function does.

Signed-off-by: Yang Li <yang.lee@linux.alibaba.com>
Link: https://lore.kernel.org/r/20230428052758.38636-1-yang.lee@linux.alibaba.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-16 19:51:24 +05:30
Krzysztof Kozlowski
2a881183dc phy: qcom-snps: correct struct qcom_snps_hsphy kerneldoc 
Update kerneldoc of struct qcom_snps_hsphy to fix:

  drivers/phy/qualcomm/phy-qcom-snps-femto-v2.c:135: warning: Function parameter or member 'update_seq_cfg' not described in 'qcom_snps_hsphy'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20230507144818.193039-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-16 19:48:55 +05:30
Neil Armstrong
b949193011 phy: amlogic: phy-meson-g12a-mipi-dphy-analog: fix CNTL2_DIF_TX_CTL0 value 
Use the same CNTL2_DIF_TX_CTL0 value used by the vendor, it was reported
fixing timings issues.

Fixes: 2a56dc650e ("phy: amlogic: Add G12A Analog MIPI D-PHY driver")
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-v4-10-2592c29ea263@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-16 19:48:10 +05:30
Tom Rix
03262a3f5b phy: mediatek: rework the floating point comparisons to fixed point 
gcc on aarch64 reports
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c: In function ‘mtk_hdmi_pll_set_rate’:
drivers/phy/mediatek/phy-mtk-hdmi-mt8195.c:240:52: error: ‘-mgeneral-regs-only’
  is incompatible with the use of floating-point types
  240 |         else if (tmds_clk >= 54 * MEGA && tmds_clk < 148.35 * MEGA)

Floating point should not be used, so rework the floating point comparisons
to fixed point.

Signed-off-by: Tom Rix <trix@redhat.com>
Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/20230502145005.2927101-1-trix@redhat.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-16 19:48:06 +05:30
David Yang
fdab47868e phy: hisilicon: Allow building phy-hisi-inno-usb2 on ARM32 
Support for inno-usb2-phy on Hi3798MV100 was added into existing driver,
while Hi3798MV100 is a A9 ARM32-only SoC.

Signed-off-by: David Yang <mmyangfl@gmail.com>
Link: https://lore.kernel.org/r/20230509060449.1151113-3-mmyangfl@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-16 19:44:29 +05:30
David Yang
3940ffc654 phy: hisilicon: Add inno-usb2-phy driver for Hi3798MV100 
Adopt existing phy-hisi-inno-usb2 driver to Hi3798MV100, with a slightly
different TEST register convention.

Signed-off-by: David Yang <mmyangfl@gmail.com>
Link: https://lore.kernel.org/r/20230509060449.1151113-2-mmyangfl@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-16 19:44:29 +05:30
Artur Weber
f64df08226 phy: Revert "phy: Remove SOC_EXYNOS4212 dep. from PHY_EXYNOS4X12_USB" 
Support for the Exynos4212 SoC was originally dropped as there were
no boards using it. We will be adding a device that uses it, so add
it back.

This reverts commit fee7e1d50c.

Signed-off-by: Artur Weber <aweber.kernel@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230501195525.6268-9-aweber.kernel@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-16 19:38:39 +05:30
Varadarajan Narayanan
a8874ada13 phy: qcom: qmp: Update IPQ9574 USB Phy initialization Sequence 
Updated USB QMP PHY Init sequence based on HPG for IPQ9574.
Reused clock and reset list from existing targets.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/4f15c21f28e2a1332fbdb04d60641cbbf05c6f15.1683630932.git.quic_varada@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-16 18:25:59 +05:30
Varadarajan Narayanan
5eaba7b5de phy: qcom-qusb2: add QUSB2 support for IPQ9574 
Add the phy init sequence for the Super Speed ports found
on IPQ9574.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/7c67e9e92227add6544009092adbd400c3cb47db.1683630932.git.quic_varada@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-16 18:25:59 +05:30
Varadarajan Narayanan
b225e9124b dt-bindings: phy: qcom,qmp-usb: Add IPQ9574 USB3 PHY 
* Add dt-bindings for USB3 PHY found on Qualcomm IPQ9574

* Making power-domains as optional since IPQ9574 doesn't have GDSCs

Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/064614c5b28f6d813634ad14a59b0bf94ac334b7.1683630932.git.quic_varada@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-16 18:25:58 +05:30
Varadarajan Narayanan
fc1ec000b6 dt-bindings: phy: qcom,qusb2: Document IPQ9574 compatible 
Document the compatible string used for the qusb2 phy in IPQ9574.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/d55c95a6bfeef3f49fdbcde9bc97157374e81a65.1683630932.git.quic_varada@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-16 18:25:58 +05:30
Daniel Machon
7a503071e0 phy: sparx5-serdes: add skip_cmu_cfg check when configuring lanes 
Add a check for skip_cmu_cfg when configuring the serdes lane.  All
individual serdeses are reset upon first configuration. Resetting the
serdes involves reconfiguring it with preset values. The serdesmode is
required to determine the clock-providing CMU, therefore make sure the
serdes is not reconfigured if the serdesmode is not set.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Link: https://lore.kernel.org/r/20230417180335.2787494-8-daniel.machon@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-08 17:13:01 +05:30
Daniel Machon
2db7289f59 phy: sparx5-serdes: remove power up of all CMUs 
CMUs should not be powered up by default anymore, so remove responsible
code.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Link: https://lore.kernel.org/r/20230417180335.2787494-7-daniel.machon@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-08 17:13:01 +05:30
Daniel Machon
96bb166425 phy: sparx5-serdes: power on CMUs individually 
Power on the CMU instance, that provides the clock for the serdes, given the
specified serdes mode and index. The CMU instance is looked up, using a
preset map of serdes mode and index to CMU index.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Link: https://lore.kernel.org/r/20230417180335.2787494-6-daniel.machon@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-08 17:13:01 +05:30
Daniel Machon
044f3a1a8d phy: sparx5-serdes: power down all CMUs by default 
All CMUs are powered up initially. This uses needless power. This patch
makes sure all CMUs are powered down by default. This involves
configuring a number reference clock and power-down registers of the
CMU.

Individual CMUs are later powered up, when the serdes lanes are
configured.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Link: https://lore.kernel.org/r/20230417180335.2787494-5-daniel.machon@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-08 17:13:01 +05:30
Daniel Machon
238a583fe4 phy: sparx5-serdes: reorder CMU functions 
Reorder CMU functions, as some of them are now required by the serdes
functions. No functional changes.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Link: https://lore.kernel.org/r/20230417180335.2787494-4-daniel.machon@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-08 17:13:01 +05:30
Daniel Machon
3d61a1f83e phy: sparx5-serdes: configure optimal quiet mode for serdes lanes 
All the serdes lanes of the sparx5 will transition between normal mode
and quiet mode, depending on activity. Make sure that the quiet mode is
configured optimally for all lanes initially. Although not much, this
will save a small amount of power.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Link: https://lore.kernel.org/r/20230417180335.2787494-3-daniel.machon@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-08 17:13:01 +05:30
Daniel Machon
86c2cfb1ab phy: sparx5-serdes: add registers required for SD/CMU power down 
Add registers required to configure serdeses and CMUs for initial power
down.

Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Link: https://lore.kernel.org/r/20230417180335.2787494-2-daniel.machon@microchip.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-08 17:13:00 +05:30
Swapnil Jakhade
72a5ce33b8 phy: cadence-torrent: Add USB + DP multilink configuration 
Add USB + DP no SSC multilink configuration sequences.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20230418173157.25607-5-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-08 17:07:01 +05:30
Swapnil Jakhade
ede775a87b phy: cadence-torrent: Add PCIe + DP multilink configuration for 100MHz refclk 
Add multilink DP configuration support for 100MHz reference clock rate.
This is the only clock rate supported currently for multilink PHY
configurations. Also, add PCIe + DP multiprotocol multilink register
configuration sequences for 100MHz refclk with no SSC.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20230418173157.25607-4-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-08 17:07:01 +05:30
Swapnil Jakhade
c756cc1621 phy: cadence-torrent: Prepare driver for multilink DP support 
This patch prepares driver for multilink DP support as well as for
multiprotocol PHY configurations involving DP as one of the required
protocols. This needs changes in functions configuring default single
link DP with master lane 0 to support non-zero master lane values and
associated PLL configurations.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20230418173157.25607-3-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-08 17:07:01 +05:30
Swapnil Jakhade
1b0524fc21 phy: cadence-torrent: Add function to get PLL to be configured for DP 
Torrent PHY PLL0 or PLL1 is used for DP depending on the single link or
multilink protocol configuration for which PHY is configured. In multilink
configurations with other protocols, either PLL0 or PLL1 will be used
for DP. For single link DP, both PLLs need to be configured at POR.

Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/20230418173157.25607-2-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-08 17:07:01 +05:30
Bartosz Golaszewski
d8c66cbbdd dt-bindings: phy: qmp-ufs: tweak clock and clock-names for sa8775p 
maxItems is already globally set to 3. To make the binding easier to read
and remove redundancy, set minItems to 3 for sa8775p as this platform
requires exactly three clocks.

Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230419120914.173715-1-brgl@bgdev.pl
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-08 15:52:50 +05:30
Krzysztof Kozlowski
d96a432cc8 dt-bindings: phy: qcom,edp-phy: allow power-domains 
At least on SC8280XP the eDP PHY is part of power domain:

  sc8280xp-crd.dtb: phy@220c2a00: 'power-domains' does not match any of the regexes: 'pinctrl-[0-9]+'

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230416151233.346336-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-08 15:48:38 +05:30
Shazad Hussain
8bd2d6e11c phy: qcom-qmp: Add SA8775P USB3 UNI phy 
The SA8775P platform has 5nm USB3 UNI phy attached to the USB0 and USB1
controllers.

Add QMP PHY config, pcs entries and support for the new compatible for
SA8775P platform.

Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230428130824.23803-5-quic_shazhuss@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-08 15:00:26 +05:30
Shazad Hussain
bfd73c859e dt-bindings: phy: qcom,sc8280xp-qmp-usb3-uni: Add SA8775P USB PHY binding 
Add compatible string for Qualcomm QMP Super Speed (SS) UNI PHY found
in SA8775P.

Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230428130824.23803-4-quic_shazhuss@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-08 15:00:26 +05:30
Shazad Hussain
66dc9a2cf5 dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for SA8775P 
Document the compatible string for USB phy found in Qualcomm SA8775P SoC

Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230428130824.23803-3-quic_shazhuss@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-08 15:00:25 +05:30
Shazad Hussain
70e5df1138 dt-bindings: usb: qcom,dwc3: Add bindings for SA8775P 
Add the compatible string for SA8775P SoC from Qualcomm.

Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230428130824.23803-2-quic_shazhuss@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-08 15:00:25 +05:30
Stanislav Jakubek
a8025faec7 dt-bindings: phy: brcm,kona-usb2-phy: convert to YAML 
Convert Broadcom Kona family USB 2.0 PHY bindings to DT schema.

Signed-off-by: Stanislav Jakubek <stano.jakubek@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230427190725.GA7730@standask-GA-A55M-S2HP
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-08 14:58:47 +05:30
Dmitry Rokosov
58247b9fed phy: amlogic: enable/disable clkin during Amlogic USB PHY init/exit 
Previously, all Amlogic boards used the XTAL clock as the default board
clock for the USB PHY input, so there was no need to enable it.
However, with the introduction of new Amlogic SoCs like the A1 family,
the USB PHY now uses a gated clock. Hence, it is necessary to enable
this gated clock during the PHY initialization sequence, or disable it
during the PHY exit, as appropriate.

Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lore.kernel.org/r/20230426102922.19705-2-ddrokosov@sberdevices.ru
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-08 14:57:37 +05:30
Johan Hovold
e42f110700 phy: qcom-qmp-pcie-msm8996: fix init-count imbalance 
The init counter is not decremented on initialisation errors, which
prevents retrying initialisation.

Add the missing decrement on initialisation errors so that the counter
reflects the state of the device.

Fixes: e78f3d15e1 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
Cc: stable@vger.kernel.org      # 4.12
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230502103810.12061-3-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-08 14:39:42 +05:30
Johan Hovold
9bf03a0cbd phy: qcom-qmp-combo: fix init-count imbalance 
The init counter is not decremented on initialisation errors, which
prevents retrying initialisation and can lead to the runtime suspend
callback attempting to disable resources that have never been enabled.

Add the missing decrement on initialisation errors so that the counter
reflects the state of the device.

Fixes: e78f3d15e1 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets")
Cc: stable@vger.kernel.org	# 4.12
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230502103810.12061-2-johan+linaro@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
 2023-05-08 14:39:42 +05:30
Linus Torvalds
ac9a78681b Linux 6.4-rc1 v6.4-rc1 2023-05-07 13:34:35 -07:00