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Connor Abbott
77beba375f drm/msm: Fix page fault client detection on a660 family and a7xx 
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/575918/
Signed-off-by: Rob Clark <robdclark@chromium.org>
 2024-02-26 07:29:55 -08:00
Connor Abbott
64d6255650 drm/msm: More fully implement devcoredump for a7xx 
Use the vendor-provided snapshot headers to dump the contextless
registers, shader blocks, and cluster registers. Still unimplemented are
the GMU registers and "external core" registers, which would require
more work because they use register spaces we don't have described in
devicetree and dump registers from multiple spaces in a single list.

Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/575919/
Signed-off-by: Rob Clark <robdclark@chromium.org>
 2024-02-26 07:29:55 -08:00
Connor Abbott
d98c220f58 drm/msm: Fix snapshotting a7xx indexed regs 
We were overwriting the last indexed reg (CP_ROQ) and we were
snapshotting the same CP_MEMPOOL block twice instead of snapshotting
CP_BV_MEMPOOL as intended.

Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/575920/
Signed-off-by: Rob Clark <robdclark@chromium.org>
 2024-02-26 07:29:55 -08:00
Connor Abbott
fadbbfbf64 drm/msm: Import a7xx crashdump register lists from kgsl 
This imports these files as-is, the following commits will have to make
slight changes to get them to compile because downstream uses
un-namespaced enums that conflict with a6xx. However we should try as
much as possible to stick to downstream's format to make importing new
gens easier.

Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/575921/
Signed-off-by: Rob Clark <robdclark@chromium.org>
 2024-02-26 07:29:54 -08:00
Neil Armstrong
d2bcca0ccc drm/msm: add support for A750 GPU 
Add support for the A750 GPU found on the SM8650 platform

Unlike the the very close A740 GPU on the SM8550 SoC, the A750 GPU
doesn't have an HWCFG block but a separate register set.

The A750 GPU info are added under the adreno_is_a750() macro and
the ADRENO_7XX_GEN3 family id.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/578693/
Signed-off-by: Rob Clark <robdclark@chromium.org>
 2024-02-26 07:29:54 -08:00
Neil Armstrong
1fdd35d59b dt-bindings: arm-smmu: Document SM8650 GPU SMMU 
Document the GPU SMMU found on the SM8650 platform.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/578685/
Signed-off-by: Rob Clark <robdclark@chromium.org>
 2024-02-26 07:29:54 -08:00
Neil Armstrong
dc94d0cc71 dt-bindings: arm-smmu: fix SM8[45]50 GPU SMMU if condition 
The if condition for the SM8[45]50 GPU SMMU is too large,
add the other compatible strings to the condition to only
allow the clocks for the GPU SMMU nodes.

Fixes: 4fff78dc24 ("dt-bindings: arm-smmu: Document SM8[45]50 GPU SMMU")
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/578686/
Signed-off-by: Rob Clark <robdclark@chromium.org>
 2024-02-26 07:29:54 -08:00
Neil Armstrong
de13192662 dt-bindings: display/msm/gmu: Document Adreno 750 GMU 
Document the Adreno 750 GMU found on the SM8650 platform.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/578684/
Signed-off-by: Rob Clark <robdclark@chromium.org>
 2024-02-26 07:29:54 -08:00
Luca Weiss
3d6ab124a4 drm/msm/adreno: Add A305B support 
Add support for the Adreno 305B GPU that is found in MSM8226(v2) SoC.
Previously this was mistakenly claimed to be supported but using wrong
a configuration.

In MSM8226v1 there's also a A305B but with chipid 0x03000510 which
should work with the same configuration but due to lack of hardware for
testing this is not added.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: David Heidelberg <david@ixit.cz>
Patchwork: https://patchwork.freedesktop.org/patch/575274/
Signed-off-by: Rob Clark <robdclark@chromium.org>
 2024-02-26 07:29:54 -08:00
Luca Weiss
0be7a75b66 dt-bindings: display/msm: gpu: Allow multiple digits for patchid 
Some GPUs like the Adreno A305B has a patchid higher than 9, in this
case 18. Make sure the regexes can account for that.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: David Heidelberg <david@ixit.cz>
Patchwork: https://patchwork.freedesktop.org/patch/575272/
Signed-off-by: Rob Clark <robdclark@chromium.org>
 2024-02-26 07:29:54 -08:00
Rob Clark
0776ad9274 drm/msm/a7xx: Fix LLC typo 
We'd miss actually activating LLC.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Fixes: af66706acc ("drm/msm/a6xx: Add skeleton A7xx support")
Patchwork: https://patchwork.freedesktop.org/patch/573043/
 2024-02-26 07:29:54 -08:00
Rob Clark
54615eda79 drm/msm/adreno: Update generated headers 
This updates the GPU headers to latest from mesa, using gen_header.py
(which is used to generate headers at bulid time for mesa), rather than
headergen2 (which doesn't have proper support for A6XX vs A7XX register
variants).

Mostly just uninteresting churn, but there are a couple spots in a7xx
paths which update REG_A6XX_foo to REG_A7XX_foo for registers which are
a7xx specific.

Cc: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/574880/
 2024-02-26 07:29:54 -08:00
Danila Tikhonov
a7165277ff drm/msm/adreno: Add support for SM7150 SoC machine 
SM7150 has 5 power levels which correspond to 5 speed-bin values: 0,
128, 146, 167, 172. Speed-bin value is calulated as FMAX/4.8MHz round up
to zero decimal places.

Also a618 on SM7150 uses a615 zapfw. Add a squashed version (.mbn).

Add this as machine = "qcom,sm7150", because speed-bin values are
different from atoll (sc7180/sm7125).

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/578902/
Signed-off-by: Rob Clark <robdclark@chromium.org>
 2024-02-26 07:29:54 -08:00
Dmitry Baryshkov
0d7dfc79fb drm/msm/a6xx: specify UBWC config for sc7180 
Historically the Adreno driver has not been updating memory
configuration registers on a618 (SC7180 platform) implying that the
default configuration is fine. After the rework performed in the commit
8814455a0e ("drm/msm: Refactor UBWC config setting") the function
a6xx_calc_ubwc_config() still contained this shortcut and did not
calculate UBWC configuration. However the function which now actually
updates hardware registers, a6xx_set_ubwc_config(), doesn't contain such
check.

Rather than adding the check to a6xx_set_ubwc_config(), fill in the
UBWC config for a618 (based on readings from SC7180).

Reported-by: Leonard Lausen <leonard@lausen.nl>
Link: https://gitlab.freedesktop.org/drm/msm/-/issues/49
Fixes: 8814455a0e ("drm/msm: Refactor UBWC config setting")
Cc: Connor Abbott <cwabbott0@gmail.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Patchwork: https://patchwork.freedesktop.org/patch/579113/
Signed-off-by: Rob Clark <robdclark@chromium.org>
 2024-02-26 07:29:54 -08:00
Abel Vesa
e3b1f369db drm/msm/dpu: Add X1E80100 support 
Add definitions for the display hardware used on the Qualcomm X1E80100
platform.

Co-developed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/579075/
Link: https://lore.kernel.org/r/20240220-x1e80100-display-v4-4-971afd9de861@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
 2024-02-22 23:23:24 +02:00
Abel Vesa
cf4d77b126 drm/msm: mdss: Add X1E80100 support 
Add support for MDSS on X1E80100.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/579079/
Link: https://lore.kernel.org/r/20240220-x1e80100-display-v4-3-971afd9de861@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
 2024-02-22 23:23:24 +02:00
Abel Vesa
81de267367 dt-bindings: display/msm: Document MDSS on X1E80100 
Document the MDSS hardware found on the Qualcomm X1E80100 platform.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/579074/
Link: https://lore.kernel.org/r/20240220-x1e80100-display-v4-2-971afd9de861@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
 2024-02-22 23:23:24 +02:00
Abel Vesa
c22d32f241 dt-bindings: display/msm: Document the DPU for X1E80100 
Document the DPU for Qualcomm X1E80100 platform in the SM8650 schema, as
they are similar.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/579072/
Link: https://lore.kernel.org/r/20240220-x1e80100-display-v4-1-971afd9de861@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
 2024-02-22 23:23:24 +02:00
Dmitry Baryshkov
ffa0c87f17 drm/msm/mdp5: drop global_state_lock 
Since the commit b962a12050 ("drm/atomic: integrate modeset lock with
private objects") the DRM framework no longer requires the external
lock for private objects. Drop the lock, letting the DRM to manage
private object locking.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/570183/
Link: https://lore.kernel.org/r/20231203000532.1290480-6-dmitry.baryshkov@linaro.org
 2024-02-19 14:10:25 +02:00
Dmitry Baryshkov
f9c27e649a drm/msm/mdp5: migrate SMP dumping to using atomic_print_state 
The Shared Memory Pool (SMP) state is a part of the MDP5's private
object state. Use existing infrastructure, atomic_print_state()
callback, to dump SMP state (which also makes it included into
debugfs/dri/N/state). This allows us to drop the custom debugfs file
too.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/570179/
Link: https://lore.kernel.org/r/20231203000532.1290480-5-dmitry.baryshkov@linaro.org
 2024-02-19 14:10:25 +02:00
Dmitry Baryshkov
abbf3108bc drm/msm/dpu: drop global_state_lock 
Since the commit b962a12050 ("drm/atomic: integrate modeset lock with
private objects") the DRM framework no longer requires the external
lock for private objects. Drop the lock, letting the DRM to manage
private object locking.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/570174/
Link: https://lore.kernel.org/r/20231203000532.1290480-4-dmitry.baryshkov@linaro.org
 2024-02-19 14:10:24 +02:00
Dmitry Baryshkov
49e27d3c9c drm/msm/dpu: finalise global state object 
Add calls to finalise global state object and corresponding lock.

Fixes: de3916c70a ("drm/msm/dpu: Track resources in global state")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/570175/
Link: https://lore.kernel.org/r/20231203000532.1290480-3-dmitry.baryshkov@linaro.org
 2024-02-19 14:10:24 +02:00
Dmitry Baryshkov
7204df5e7e drm/msm/dpu: add support for SDM660 and SDM630 platforms 
Bring in hardware support for the SDM660 and SDM630 platforms, which
belong to the same DPU generation as MSM8998.

Note, by default these platforms are still handled by the MDP5 driver
unless the `msm.prefer_mdp5=false' parameter is provided.

Co-developed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/577507/
Link: https://lore.kernel.org/r/20240208-fd-migrate-mdp5-v4-4-945d08ef3fa8@linaro.org
 2024-02-19 13:39:40 +02:00
Dmitry Baryshkov
b8b1231870 drm/msm: add a kernel param to select between MDP5 and DPU drivers 
For some of the platforms (e.g. SDM660, SDM630, MSM8996, etc.) it is
possible to support this platform via the DPU driver (e.g. to provide
support for DP, multirect, etc). Add a modparam to be able to switch
between these two drivers.

All platforms supported by both drivers are by default handled by the
MDP5 driver. To let them be handled by the DPU driver pass the
`msm.prefer_mdp5=false` kernel param.

Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Carl Vanderlip <quic_carlv@quicinc.com>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/577504/
Link: https://lore.kernel.org/r/20240208-fd-migrate-mdp5-v4-3-945d08ef3fa8@linaro.org
 2024-02-19 13:39:39 +02:00
Dmitry Baryshkov
39b06ed6d4 drm/msm/dpu: support binding to the mdp5 devices 
Existing MDP5 devices have slightly different bindings. The main
register region is called `mdp_phys' instead of `mdp'. Also vbif
register regions are a part of the parent, MDSS device. Add support for
handling this binding differences.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/577505/
Link: https://lore.kernel.org/r/20240208-fd-migrate-mdp5-v4-2-945d08ef3fa8@linaro.org
 2024-02-19 13:39:39 +02:00
Dmitry Baryshkov
d2570ee67a drm/msm/mdss: generate MDSS data for MDP5 platforms 
Older (mdp5) platforms do not use per-SoC compatible strings. Instead
they use a single compat entry 'qcom,mdss'. To facilitate migrating
these platforms to the DPU driver provide a way to generate the MDSS /
UBWC data at runtime, when the DPU driver asks for it.

It is not possible to generate this data structure at the probe time,
since some platforms might not have MDP_CLK enabled, which makes reading
HW_REV register useless and prone to possible crashes.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/577502/
Link: https://lore.kernel.org/r/20240208-fd-migrate-mdp5-v4-1-945d08ef3fa8@linaro.org
 2024-02-19 13:39:39 +02:00
Colin Ian King
fb750eefc4 drm/msm/dp: Fix spelling mistake "enale" -> "enable" 
There is a spelling mistake in a drm_dbg_dp message. Fix it.

Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/577760/
Link: https://lore.kernel.org/r/20240212091639.2397424-1-colin.i.king@gmail.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
 2024-02-19 13:39:23 +02:00
Dmitry Baryshkov
3b56d27ba1 drm/msm/dsi: Document DSC related pclk_rate and hdisplay calculations 
Provide actual documentation for the pclk and hdisplay calculations in
the case of DSC compression being used.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/577534/
Link: https://lore.kernel.org/r/20240208-fd_document_dsc_pclk_rate-v4-1-56fe59d0a2e0@linaro.org
 2024-02-11 22:38:08 +02:00
Dmitry Baryshkov
b0b621f41b drm/msm/dpu: drop dpu_encoder_phys_ops::atomic_check() 
Writeback was the last user of dpu_encoder_phys_ops's atomic_check()
callback. As the code was moved to the dpu_writeback.c, the callback
becomes unused. Drop it now.

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/577528/
Link: https://lore.kernel.org/r/20240208-fd_remove_phys_ops_atomic_mode_set-v4-5-caf5dcd125c0@linaro.org
 2024-02-11 22:38:08 +02:00
Dmitry Baryshkov
71174f362d drm/msm/dpu: move writeback's atomic_check to dpu_writeback.c 
dpu_encoder_phys_wb is the only user of encoder's atomic_check callback.
Move corresponding checks to drm_writeback_connector's implementation
and drop the dpu_encoder_phys_wb_atomic_check() function.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Tested-by: Paloma Arellano <quic_parellan@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/577524/
Link: https://lore.kernel.org/r/20240208-fd_remove_phys_ops_atomic_mode_set-v4-4-caf5dcd125c0@linaro.org
 2024-02-11 22:38:08 +02:00
Dmitry Baryshkov
d13f638c9b drm/msm/dpu: drop dpu_encoder_phys_ops.atomic_mode_set 
The atomic_mode_set() callback only sets the phys_enc's IRQ data. As the
INTF and WB are statically allocated to each encoder/phys_enc, drop the
atomic_mode_set callback and set the IRQs during encoder init.

For the CMD panel usecase some of IRQ indexes depend on the selected
resources. Move setting them to the irq_enable() callback.

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Tested-by: Abhinav Kumar <quic_abhinavk@quicinc.com> # sc7280
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/577529/
Link: https://lore.kernel.org/r/20240208-fd_remove_phys_ops_atomic_mode_set-v4-3-caf5dcd125c0@linaro.org
 2024-02-11 22:38:08 +02:00
Dmitry Baryshkov
ca8c1fd3ee drm/msm/dpu: split _dpu_encoder_resource_control_helper() 
Follow the _dpu_encoder_irq_control() change and split the
_dpu_encoder_resource_control_helper() into enable and disable parts.

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/577525/
Link: https://lore.kernel.org/r/20240208-fd_remove_phys_ops_atomic_mode_set-v4-2-caf5dcd125c0@linaro.org
 2024-02-11 22:38:08 +02:00
Dmitry Baryshkov
c6f60037bf drm/msm/dpu: split irq_control into irq_enable and _disable 
The single helper for both enable and disable cases is too complicated,
especially if we start adding more code to these helpers. Split it into
irq_enable and irq_disable cases.

Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/577526/
Link: https://lore.kernel.org/r/20240208-fd_remove_phys_ops_atomic_mode_set-v4-1-caf5dcd125c0@linaro.org
 2024-02-11 22:38:08 +02:00
Marijn Suijten
06267d22f9 drm/msm/dpu: Only enable DSC_MODE_MULTIPLEX if dsc_merge is enabled 
When the topology calls for two interfaces on the current fixed topology
of 2 DSC blocks, or uses 1 DSC block for a single interface (e.g. SC7280
with only one DSC block), there should be no merging of DSC output.

This is already represented by the return value of
dpu_encoder_use_dsc_merge(), but not yet used to correctly configure
this flag.

Fixes: 58dca98107 ("drm/msm/disp/dpu1: Add support for DSC in encoder")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/577067/
Link: https://lore.kernel.org/r/20240204-dpu-dsc-multiplex-v1-1-080963233c52@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
 2024-02-11 22:38:08 +02:00
Marijn Suijten
99d519fed7 drm/msm/dsi: Replace dsi_get_bpp() with mipi_dsi header function 
drm_mipi_dsi.h already provides a conversion function from MIPI_DSI_FMT_
to bpp, named mipi_dsi_pixel_format_to_bpp().

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/577065/
Link: https://lore.kernel.org/r/20240204-drm-msm-dsi-remove-open-coded-get-bpp-v1-1-c16212de7e86@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
 2024-02-11 22:38:07 +02:00
Rob Herring
4825b20700 dt-bindings: display: msm: sm8650-mdss: Add missing explicit "additionalProperties" 
In order to check schemas for missing additionalProperties or
unevaluatedProperties, cases allowing extra properties must be explicit.

Signed-off-by: Rob Herring <robh@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/576954/
Link: https://lore.kernel.org/r/20240202222338.1652333-1-robh@kernel.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
 2024-02-11 22:38:07 +02:00
Abhinav Kumar
2f4a67a389 drm/msm/dpu: fix the programming of INTF_CFG2_DATA_HCTL_EN 
Currently INTF_CFG2_DATA_HCTL_EN is coupled with the enablement
of widebus but this is incorrect because we should be enabling
this bit independent of widebus except for cases where compression
is enabled in one pixel per clock mode.

Fix this by making the condition checks more explicit and enabling
INTF_CFG2_DATA_HCTL_EN for all other cases when supported by DPU.

Fixes: 3309a75639 ("drm/msm/dpu: revise timing engine programming to support widebus feature")
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/576722/
Link: https://lore.kernel.org/r/20240201004737.2478-1-quic_abhinavk@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
 2024-02-11 22:38:07 +02:00
Dmitry Baryshkov
6215f1558b drm/msm/dp: drop dp_parser 
Finally drop separate "parsing" submodule. There is no need in it
anymore. All submodules handle DT properties directly rather than
passing them via the separate structure pointer.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/576116/
Link: https://lore.kernel.org/r/20240126-dp-power-parser-cleanup-v3-15-098d5f581dd3@linaro.org
 2024-02-11 22:38:07 +02:00
Dmitry Baryshkov
b3b1d122a8 drm/msm/dp: move next_bridge handling to dp_display 
Remove two levels of indirection and fetch next bridge directly in
dp_display_probe_tail().

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/576126/
Link: https://lore.kernel.org/r/20240126-dp-power-parser-cleanup-v3-14-098d5f581dd3@linaro.org
 2024-02-11 22:38:07 +02:00
Dmitry Baryshkov
3ffe15b30a drm/msm/dp: move link property handling to dp_panel 
Instead of passing link properties through the separate struct, parse
them directly in the dp_panel.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/576117/
Link: https://lore.kernel.org/r/20240126-dp-power-parser-cleanup-v3-13-098d5f581dd3@linaro.org
 2024-02-11 22:38:07 +02:00
Dmitry Baryshkov
1577814118 drm/msm/dp: move all IO handling to dp_catalog 
Rather than parsing the I/O addresses from dp_parser and then passing
them via a struct pointer to dp_catalog, handle I/O region parsing in
dp_catalog and drop it from dp_parser.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/576108/
Link: https://lore.kernel.org/r/20240126-dp-power-parser-cleanup-v3-12-098d5f581dd3@linaro.org
 2024-02-11 22:38:07 +02:00
Dmitry Baryshkov
f304bda5bf drm/msm/dp: handle PHY directly in dp_ctrl 
There is little point in going trough dp_parser->io indirection each
time the driver needs to access the PHY. Store the pointer directly in
dp_ctrl_private.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/576119/
Link: https://lore.kernel.org/r/20240126-dp-power-parser-cleanup-v3-11-098d5f581dd3@linaro.org
 2024-02-11 22:38:07 +02:00
Dmitry Baryshkov
64eba0d63c drm/msm/dp: remove PHY handling from dp_catalog.c 
Inline dp_catalog_aux_update_cfg() and call phy_calibrate() from dp_aux
functions directly.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/576106/
Link: https://lore.kernel.org/r/20240126-dp-power-parser-cleanup-v3-10-098d5f581dd3@linaro.org
 2024-02-11 22:38:07 +02:00
Dmitry Baryshkov
b4745f741e drm/msm/dp: move phy_configure_opts to dp_ctrl 
There is little point in sharing phy configuration structure between
several modules. Move it to dp_ctrl, which becomes the only submodule
re-configuring the PHY.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Tested-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/576124/
Link: https://lore.kernel.org/r/20240126-dp-power-parser-cleanup-v3-9-098d5f581dd3@linaro.org
 2024-02-11 22:38:07 +02:00
Dmitry Baryshkov
e518c27218 drm/msm/dp: split dp_ctrl_clk_enable into four functuions 
Split the dp_ctrl_clk_enable() beast into four functions, each of them
doing just a single item: enabling or disabling core or link clocks.
This allows us to cleanup the dss_module_power structure and makes
several dp_ctrl functions return void.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/576105/
Link: https://lore.kernel.org/r/20240126-dp-power-parser-cleanup-v3-8-098d5f581dd3@linaro.org
 2024-02-11 22:38:07 +02:00
Dmitry Baryshkov
77d0243a33 drm/msm/dp: stop parsing clock names from DT 
All supported platforms use the same clocks configuration. Instead of
parsing names from DT in a pretty complex manner, use the static
configuration. If at some point newer (or older) platforms have
different clock configuration, this clock config can be moved to the
device data.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/576115/
Link: https://lore.kernel.org/r/20240126-dp-power-parser-cleanup-v3-7-098d5f581dd3@linaro.org
 2024-02-11 22:38:07 +02:00
Dmitry Baryshkov
9bd0946d5c drm/msm/dp: simplify stream clocks handling 
There is only a single DP_STREAM_PM clock, stream_pixel. Instead of
using a separate dss_module_power instance for this single clock, handle
this clock directly. This allows us to drop several wrapping functions.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/576102/
Link: https://lore.kernel.org/r/20240126-dp-power-parser-cleanup-v3-6-098d5f581dd3@linaro.org
 2024-02-11 22:38:07 +02:00
Dmitry Baryshkov
17cb153f81 drm/msm/dp: fold dp_power into dp_ctrl module 
The dp_power submodule is limited to handling the clocks only following
previous cleanups. Fold it into the dp_ctrl submodule, removing one
unnecessary level of indirection.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/576104/
Link: https://lore.kernel.org/r/20240126-dp-power-parser-cleanup-v3-5-098d5f581dd3@linaro.org
 2024-02-11 22:38:07 +02:00
Dmitry Baryshkov
47103b5824 drm/msm/dp: inline dp_power_(de)init 
In preparation to cleanup of the dp_power module, inline dp_power_init()
and dp_power_deinit() functions, which are now just turning the clocks
on and off.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/576113/
Link: https://lore.kernel.org/r/20240126-dp-power-parser-cleanup-v3-4-098d5f581dd3@linaro.org
 2024-02-11 22:38:07 +02:00
Dmitry Baryshkov
31a01db14b drm/msm/dp: parse DT from dp_parser_get 
It makes little sense to split the submodule get and actual DT parsing.
Call dp_parser_parse() directly from dp_parser_get(), so that the parser
data is fully initialised once it is returned to the caller.

Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/576101/
Link: https://lore.kernel.org/r/20240126-dp-power-parser-cleanup-v3-3-098d5f581dd3@linaro.org
 2024-02-11 22:38:07 +02:00