* clk-qcom-sdm845:
clk: qcom: Export clk_fabia_pll_configure()
clk: qcom: Add video clock controller driver for SDM845
dt-bindings: clock: Introduce QCOM Video clock bindings
clk: qcom: Add Global Clock controller (GCC) driver for SDM845
clk: qcom: Add DT bindings for SDM845 gcc clock controller
clk: qcom: Configure the RCGs to a safe source as needed
clk: qcom: Add support for BRANCH_HALT_SKIP flag for branch clocks
clk: qcom: Simplify gdsc status checking logic
clk: qcom: gdsc: Add support to poll CFG register to check GDSC state
clk: qcom: gdsc: Add support to poll for higher timeout value
clk: qcom: gdsc: Add support to reset AON and block reset logic
clk: qcom: Add support for controlling Fabia PLL
clk: qcom: Clear hardware clock control bit of RCG
Also fixup the Kconfig mess where SDM845 GCC has msm8998 in the
description and also the video Kconfig says things slightly differently
from the GCC one so just make it the same.
* clk-match-string:
clk: use match_string() helper
clk: bcm2835: use match_string() helper
* clk-ingenic:
clk: ingenic: jz4770: Add 150us delay after enabling VPU clock
clk: ingenic: jz4770: Enable power of AHB1 bus after ungating VPU clock
clk: ingenic: jz4770: Modify C1CLK clock to disable CPU clock stop on idle
clk: ingenic: jz4770: Change OTG from custom to standard gated clock
clk: ingenic: Support specifying "wait for clock stable" delay
clk: ingenic: Add support for clocks whose gate bit is inverted
* clk-si544-round-fix:
clk-si544: Properly round requested frequency to nearest match
* clk-bcm-stingray:
clk: bcm: Update and add Stingray clock entries
dt-bindings: clk: Update Stingray binding doc
* clk-imx7d:
clk: imx7d: reset parent for mipi csi root
clk: imx7d: fix mipi dphy div parent
* clk-hisi-stub:
clk/driver/hisi: Consolidate the Kconfig for the CLOCK_STUB
* clk-mvebu:
clk: mvebu: use correct bit for 98DX3236 NAND
* clk-imx6-epit:
clk: imx6: add EPIT clock support
* clk-debugfs-simple:
clk: Return void from debug_init op
clk: remove clk_debugfs_add_file()
clk: tegra: no need to check return value of debugfs_create functions
clk: davinci: no need to check return value of debugfs_create functions
clk: bcm2835: no need to check return value of debugfs_create functions
clk: no need to check return value of debugfs_create functions
* clk-qcom-rpmh:
dt-bindings: clock: Introduce QCOM RPMh clock bindings
* clk-npcm7xx:
clk: npcm7xx: fix return value check in npcm7xx_clk_init()
clk: npcm7xx: add clock controller
dt-binding: clk: npcm750: Add binding for Nuvoton NPCM7XX Clock
* clk-of-parent-count:
pinctrl: sunxi: Use of_clk_get_parent_count() instead of open coding
soc/tegra: pmc: Use of_clk_get_parent_count() instead of open coding
soc: rockchip: power-domain: Use of_clk_get_parent_count() instead of open coding
ARM: timer-sp: Use of_clk_get_parent_count() instead of open coding
clk: Extract OF clock helpers in <linux/of_clk.h>
* clk-qcom-rcg-fix:
clk: qcom: Base rcg parent rate off plan frequency
This is used by the video clk driver on sdm845 and that's a module.
Export it to prevent module build failures.
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Update and add Stingray clock definitions and tables so they match the
binding document and the latest ASIC datasheet
Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Update Stingray clock binding document to add additional clock entries
with names matching the latest ASIC datasheet. Also modify a few existing
entries to make their naming more consistent with the rest of the entries
Signed-off-by: Pramod Kumar <pramod.kumar@broadcom.com>
Signed-off-by: Ray Jui <ray.jui@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The si544 driver had a rounding problem that using the result of clk_round_rate
may set the clock to yet another rate, for example:
clk_round_rate(195000000) = 194999999
clk_round_rate(194999999) = 194999998
Clients would expect that after clk_set_rate(clk, freq2=clk_round_rate(clk, freq)) the
chip will be running at exactly freq2.
The problem was in the calculation of the feedback divider, it was always rounded
down instead of to the nearest possible VCO value.
After this change, the following holds true for any supported frequency:
actual_freq = clk_round_rate(clk, freq);
clk_set_rate(clk, actual_freq);
clk_round_rate(clk, actual_freq) == actual_freq && clk_get_rate(clk) == actual_freq
Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Fixes: 953cc3e811 ("clk: Add driver for the si544 clock generator chip")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This is required, as we must not use the AHB1 bus before it is stable.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This was broken before, because the AHB1 bus was enabled before the VPU
clock was ungated, while it must be done afterwards.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
When the main processor goes idle, by default its clock is stopped.
However, this also stops the clock of the co-processor.
Here, if the C1CLK clock is enabled, we disable this functionality.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
We now have the means to express the specificities of the OTG clock with
the common CGU code.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Some clocks need a small delay after being ungated to run stable, as
using them too soon might result in hardware lockups.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Support the clocks which are gated when their gate bit is cleared
instead of set.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
We only have two users of the debug_init hook, and we recently stopped
caring about the return value from that op. Finish that off by changing
the clk_op to return void instead of int because it doesn't matter if
debugfs fails or not.
Cc: Eric Anholt <eric@anholt.net>
Cc: David Lechner <david@lechnology.com>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
When calling debugfs functions, there is no need to ever check the
return value. The function can work or not, but the code logic should
never do something different based on this.
The return value of these functions were never checked in the end
anyway, so it is obvious this does not change any functionality :)
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
When calling debugfs functions, there is no need to ever check the
return value. The function can work or not, but the code logic should
never do something different based on this.
Acked-by: David Lechner <david@lechnology.com>
Cc: Sekhar Nori <nsekhar@ti.com>
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
When calling debugfs functions, there is no need to ever check the
return value. The function can work or not, but the code logic should
never do something different based on this.
This cleans up the init code a lot, and there's no need to return an
error value based on the debugfs calls, especially as it turns out no
one was even looking at that return value. So it obviously wasn't that
important :)
Cc: Michael Turquette <mturquette@baylibre.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The correct fieldbit value for the NAND PLL reload trigger is 27.
Fixes: commit e120c17a70 ("clk: mvebu: support for 98DX3236 SoC")
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The current defconfig is inconsistent as it selects the mailbox and
the clock for the hi6220 and the hi3660 without having their Kconfigs
making sure the dependencies are correct. It ends up when selecting
different versions for the kernel (for example when git bisecting)
those options disappear and they don't get back, leading to unexpected
behaviors. In our case, the cpufreq driver does no longer work because
the clock fails to initialize due to the clock stub and the mailbox
missing.
In order to have the dependencies correctly set when defaulting, let's
do the same as commit 3a49afb84c ("clk: enable hi655x common clk
automatically") where we select automatically the driver when the
parent driver is selected. With sensible defaults in place, we can leave
other choices for EXPERT.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
To guarantee that we do not get Overflow in image FIFO the outer bandwidth has
to be faster than inputer bandwidth. For that it must be possible to set a
faster frequency clock. So set new parent to sys_pfd3 clock for the mipi csi
block.
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
ENET "ipg" clock should be IMX7D_ENETx_IPG_ROOT_CLK
rather than IMX7D_ENET_AXI_ROOT_CLK which is for ENET bus
clock.
Based on Andy Duan's patch from the NXP kernel tree.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Correct enet clock gates as below:
CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 and enet2 bus clocks)
CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK
CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK
Just rename unused IMX7D_ENETx_REF_ROOT_CLK for
IMX7D_ENETx_IPG_ROOT_CLK instead of adding new clocks.
Based on Andy Duan's patch from the NXP kernel tree.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
IMX7D_ENET_PHY_REF_ROOT_DIV supplies clock for PHY directly,
there is no clock gate after it, rename it to
IMX7D_ENET_PHY_REF_ROOT_CLK to avoid device tree change.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
IMX6SL_CLK_OCRAM_PODF is a busy divider, its name in
CCM_CDHIPR register of Reference Manual CCM chapter
is axi_podf_busy, correct its clock type.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Disable those unnecessary clocks during kernel boot up to save power,
those modules clock should be managed by modules driver in runtime.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for the video clock controller found on SDM845
based devices. This would allow video drivers to probe and
control their clocks.
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add device tree bindings for video clock controller for
Qualcomm Technology Inc's SoCs.
Signed-off-by: Amit Nischal <anischal@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
There's no bus infrastructure today to handle all the mmagic bus
clocks and GDSCs needed by all the multimedia blocks in msm8996, like
mdss, video, camera and gpu. Mark all these clocks with a CLK_IS_CRITICAL
and GDSCs with a ALWAYS_ON flag for now so they are left always enabled.
This patch should be reverted at some point when we do have a bus driver
to manage these clocks and GDSCs.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
We have atleast some instances of ALWAYS_ON gdscs, which need to
be turned ON *before* some clocks within the gdsc domain marked
with a CLK_IS_CRITICAL can be turned ON.
To facilitate this sequence, register the GDCSs (and hence handle
the ALWAYS_ON gdscs) before we register clocks (and handle the
clocks marked as CLK_IS_CRITICAL)
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Some GDSCs might have software control to turn them off, but we might
want to keep them enabled always, in some cases because of lack of
support in kernel to handle a graceful turning off/on of such GDSCs.
Most common instances would be the GDCSs which power up the noc/bus
fabrics, which need bus drivers to handle them and atleast support for
which is missing on all qcom SoCs.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Use the appropriate SPDX license identifier and drop the previous
license text.
Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Pull Tegra clk driver updates from Thierry Reding:
- proper implementation of the CDEV1/2 clocks on Tegra20
* tag 'tegra-for-4.18-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20
clk: tegra20: Correct parents of CDEV1/2 clocks
clk: tegra20: Add DEV1/DEV2 OSC dividers
Pull rockchip clk driver updates from Heiko Stuebner:
Conversion to match_string helper of open-coded string comparison
and removal of the initial devicetree-based gate-clocks, which were
deprecated since 2014.
* tag 'v4.18-rockchip-clk-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
clk: rockchip: remove deprecated gate-clk code and dt-binding
clk: rockchip: use match_string() helper
Pull Allwinner clock changes from Maxime Ripard:
Not a lot of changes for this release, but two quite important features
were added: the H6 PRCM clock support, and the needed changes to the R40
clock driver to allow for the EMAC to operate.
* tag 'sunxi-clk-for-4.18' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
clk: sunxi-ng: r40: export a regmap to access the GMAC register
clk: sunxi-ng: r40: rewrite init code to a platform driver
clk: sunxi-ng: add support for H6 PRCM CCU
Initially we tried modeling clocks via the devicetree before switching
to clocks declared in the clock drivers and only exporting specific
ids to the devicetree.
As the old code was in the kernel for 1-2 releases when the new mode
of operation was added we kept it for backwards compatibility.
That deprecation notice is in the binding since july 2014, so nearly
4 years now and I think it's time to drop the old cruft.
Especially as at the time using the mainline kernel on Rockchip devices
was not really possible, except for experiments on the really old socs of
the rk3066 + rk3188 line, so there shouldn't be any devicetrees still
around that rely on that code.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
