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Author SHA1 Message Date
AngeloGioacchino Del Regno
6f0d2e07f2 clk: mediatek: Allow building most MT6797 clock drivers as modules 
Most of the MT6797 clock drivers can be built as modules: change them
to tristate to allow that.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-46-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:17 -07:00
AngeloGioacchino Del Regno
cfe2c864f0 clk: mediatek: Allow building most MT6765 clock drivers as modules 
Most of the MT6765 clock drivers can be built as modules: change them
to tristate to allow that.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-45-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:17 -07:00
AngeloGioacchino Del Regno
95ffe65437 clk: mediatek: Allow all MT8183 clocks to be built as modules 
All MT8183 clocks are platform drivers now! Allow module build for
all of them.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-44-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:17 -07:00
AngeloGioacchino Del Regno
a851b17059 clk: mediatek: Allow all MT8167 clocks to be built as modules 
Almost all MT8167 clocks have been converted to use the common probe
mechanism, moreover, now all of them are platform drivers: allow
building as modules.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-43-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:17 -07:00
AngeloGioacchino Del Regno
c8f0ef9973 clk: mediatek: Allow MT7622 clocks to be built as modules 
Now that all drivers are using the simple probe mechanism change the
MT7622 clock drivers to tristate in Kconfig to allow module build.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-42-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:17 -07:00
AngeloGioacchino Del Regno
e55351ac27 clk: mediatek: Allow building MT8192 non-critical clocks as modules 
Allow building non boot critical clocks for MT8192 SoC as modules by
changing them to tristate.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-41-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:17 -07:00
AngeloGioacchino Del Regno
0f471d31e5 clk: mediatek: Split MT8195 clock drivers and allow module build 
MT8195 clock drivers were encapsulated in one single (and big) Kconfig
option: there's no reason to do that, as it is totally unnecessary to
build in all or none of them.

Split them out: keep boot-critical clocks as bool and allow choosing
non critical clocks as tristate.

As a note, the dependencies of VDEC/VENCSYS and CAM/IMG/IPE/WPESYS
are not for build-time but rather for runtime, as clocks registered
by those have runtime dependencies on either or both VPP and IMGSYS.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-40-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:17 -07:00
AngeloGioacchino Del Regno
650fcdf918 clk: mediatek: mt2712: Change Kconfig options to allow module build 
All of the mt2712 drivers have been converted to platform drivers!
Change the Kconfig options for all MT2712 clocks to tristate to allow
building all clock drivers as modules.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-39-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:17 -07:00
AngeloGioacchino Del Regno
a451da86cf clk: mediatek: Add MODULE_LICENSE() where missing 
In order to successfully build clock drivers as modules it is required
to declare a module license: add it where missing.
While at it, also change the MODULE_LICENSE text from "GPL v2" to
"GPL" (which means the same) on clk-mt7981-eth.c.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks
Link: https://lore.kernel.org/r/20230306140543.1813621-38-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:16 -07:00
AngeloGioacchino Del Regno
164d240de9 clk: mediatek: Switch to module_platform_driver() where possible 
Lots of clock drivers have got both .probe() and a .remove() callbacks:
switch from builtin_platform_driver() to module_platform_driver() so
that we actually register the .remove() callback.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks
Link: https://lore.kernel.org/r/20230306140543.1813621-37-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:16 -07:00
AngeloGioacchino Del Regno
c5f34f63e5 clk: mediatek: mt8186-mcu: Migrate to common probe mechanism 
Convert MT8186 MCUSYS clocks to the common mtk_clk_simple_probe().

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-36-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:16 -07:00
AngeloGioacchino Del Regno
1d04e30065 clk: mediatek: mt7986-eth: Migrate to common probe mechanism 
Convert this driver to use the common mtk_clk_simple_probe() mechanism.
While at it, also remove __initconst annotations (as these structures
are used also at runtime).

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-35-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:16 -07:00
AngeloGioacchino Del Regno
148a39560b clk: mediatek: mt7986-infracfg: Migrate to common probe mechanism 
Convert this driver to use the common mtk_clk_simple_probe() mechanism.
While at it, also use module_platform_driver() instead, as this driver
just gained a .remove() callback during the conversion.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-34-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:16 -07:00
AngeloGioacchino Del Regno
2562dc42ae clk: mediatek: mt7986-apmixed: Use PLL_AO flag to set critical clock 
Instead of calling clk_prepare_enable() at probe time, add the PLL_AO
flag to CLK_APMIXED_ARMPLL clock: this will set CLK_IS_CRITICAL.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Daniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-33-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:16 -07:00
AngeloGioacchino Del Regno
6b7daeaa7e clk: mediatek: Propagate struct device with mtk_clk_register_dividers() 
Propagate struct device for divider clocks registered through clk-mtk
helpers to be able to get runtime PM support for MTK clocks.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks
Link: https://lore.kernel.org/r/20230306140543.1813621-32-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:16 -07:00
AngeloGioacchino Del Regno
876d4e21aa clk: mediatek: mt8516: Allow building clock drivers as modules 
Now that all MT8516 drivers have been converted to platform driver,
change the configuration options to tristate.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-31-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:16 -07:00
AngeloGioacchino Del Regno
b8390192f2 clk: mediatek: mt8516: Convert to platform driver and simple probe 
Convert the MT8516 clock drivers to be platform drivers and use the
common probe mechanism.

Thanks to the conversion, more error handling was added to the clocks
registration.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-30-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:16 -07:00
AngeloGioacchino Del Regno
f419069ad8 clk: mediatek: mt8516: Move apmixedsys clock driver to its own file 
In preparation for migrating mt8516 clocks to the common simple
probe mechanism, convert the apmixedsys to be a separated
platform driver and move it to clk-mt8516-apmixedsys.c.
While at it, also fix some indentation issues.

During the conversion, error handling was added to the apmixedsys
probe function.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-29-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:15 -07:00
AngeloGioacchino Del Regno
054a47fc47 clk: mediatek: mt7622: Convert to platform driver and simple probe 
Convert the MT7622 topckgen and pericfg clock drivers to platform
drivers and use the simple probe mechanism. This also allows to
build these clocks as modules.

Thanks to the conversion, more error handling was added to the clocks
registration.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-28-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:15 -07:00
AngeloGioacchino Del Regno
838b86331c clk: mediatek: mt7622: Move infracfg to clk-mt7622-infracfg.c 
The infracfg driver cannot be converted to clk_mtk_simple_probe() as
it registers cpumuxes, which is not supported on the common probing
mechanism: for this reason, move it to its own file.
While at it, also convert it to be a platform driver instead; to do
so, also add a .remove() callback for this driver.

During the conversion, error handling was added to the infracfg
probe function.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-27-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:15 -07:00
AngeloGioacchino Del Regno
c50e2ea650 clk: mediatek: mt7622-apmixedsys: Add .remove() callback for module build 
Add a .remove() callback to the apmixedsys driver to allow full module
build; while at it, also change the usage of builtin_platform_driver()
to module_platform_driver() to actually make use of the new callback.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-26-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:15 -07:00
AngeloGioacchino Del Regno
9aed98adf6 clk: mediatek: mt7622: Move apmixedsys clock driver to its own file 
In preparation for migrating mt7622 clocks to the common simple
probe mechanism, move apmixedsys clocks to a different file.
While at it, use the builtin_platform_driver() macro for it.

During the conversion, error handling was added to the apmixedsys
probe function.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-25-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:15 -07:00
AngeloGioacchino Del Regno
fa8c0d01df clk: mediatek: mt7622: Properly use CLK_IS_CRITICAL flag 
Instead of calling clk_prepare_enable() for clocks that shall stay
enabled, use the CLK_IS_CRITICAL flag, which purpose is exactly that.

Fixes: 2fc0a509e4 ("clk: mediatek: add clock support for MT7622 SoC")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-24-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:15 -07:00
AngeloGioacchino Del Regno
4c85e20b65 clk: mediatek: Consistently use GATE_MTK() macro 
All the various MediaTek clock drivers are, in a way or another,
redefining the GATE_MTK() macro with different names: while some
are doing that by actually using GATE_MTK(), others are copying
it entirely (hence, entirely redefining it).

Change all clock drivers to always and consistently use this macro.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org> # MT8183, MT8192, MT8195 Chromebooks
Link: https://lore.kernel.org/r/20230306140543.1813621-23-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:15 -07:00
AngeloGioacchino Del Regno
3f37ba7cc3 clk: mediatek: mt8183: Convert all remaining clocks to common probe 
Switch to mtk_clk_simple_{probe,remove}() for infracfg and topckgen
clocks on MT8183 to allow full module build for clock drivers.

Differently from other MediaTek clock drivers, it was necessary to
change the name of the `clk13m` clock, as that is already declared
in the SoC's devicetree as a "fixed-factor-clock" (with the same
name) and redeclaring it here would obviously fail to register the
entire clock controller; this clock wasn't dropped only to retain
compatibility with older devicetrees

As a note, the `clk13m` clock is not mentioned in any parent names
array(s) as the correct one (csw_f26m_d2) is already used in place
of that.

Thanks to the conversion, more error handling was added to the clocks
registration.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-22-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:15 -07:00
AngeloGioacchino Del Regno
2f140dabfe clk: mediatek: mt8183: Compress clocks arrays entries where possible 
Increase human readability and decrease number of lines by compressing
the clock array entries where possible, to a maximum of ~95 columns.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-21-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:15 -07:00
AngeloGioacchino Del Regno
127fadf7a4 clk: mediatek: mt8183: Move apmixedsys clock driver to its own file 
In preparation for migrating all other mt8183 clocks to the common
mtk_clk_simple_probe(), move apmixedsys clocks to a different file.
While at it, use the builtin_platform_driver() macro for it and fix
some indentation issues in the PLLs table.

During the conversion, error handling was added to the apmixedsys
probe function.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-20-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:14 -07:00
AngeloGioacchino Del Regno
beb47f1942 clk: mediatek: mt8167: Convert to mtk_clk_simple_{probe,remove}() 
Convert topckgen and infracfg clock drivers to use the common
mtk_clk_simple_probe() mechanism and change this from the old
"static" CLK_OF_DECLARE to be a platform driver, allowing it
to eventually be built as a module.

Thanks to the conversion, more error handling was added to the clocks
registration.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-19-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:14 -07:00
AngeloGioacchino Del Regno
b4bd678f27 clk: mediatek: mt8167: Remove __initconst annotation from arrays 
In preparation for converting the MT8167 clock drivers to be proper
platform_driver(s), drop the __initconst annotation from all of the
clock arrays since they will be used not only during init but also
during runtime.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-18-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:14 -07:00
AngeloGioacchino Del Regno
b27284336a clk: mediatek: mt8167: Move apmixedsys as platform_driver in new file 
In preparation for migrating all other MT8167 clocks to the common
mtk_clk_simple_probe(), move apmixedsys clocks to a different file.
While at it, also migrate away from the legacy CLK_OF_DECLARE and
convert this clock driver to be a platform_driver instead.

During the conversion, error handling was added to the apmixedsys
probe function.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-17-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:14 -07:00
AngeloGioacchino Del Regno
c1a988f15a clk: mediatek: mt8167: Compress GATE_TOPx macros 
Use the GATE_MTK macro to compress the GATE_TOP{0..5} macros.
No functional changes.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-16-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:14 -07:00
AngeloGioacchino Del Regno
ffe91cb28f clk: mediatek: mt8365: Convert to mtk_clk_simple_{probe,remove}() 
All clocks in this driver are supported by the common simple probe
mechanism and it's now possible to migrate to it.

While at it, also switch to using the module_platform_driver() macro.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-15-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:14 -07:00
AngeloGioacchino Del Regno
ff96210073 clk: mediatek: mt8365: Join top_misc_mux_gates and top_misc_muxes arrays 
In preparation for migrating this driver to the simple probe mechanism,
join the audio gates to the top_misc_mux_gates array of mtk_composite
clocks in one top_misc_muxes array.

While at it, since the `apll_i2s0_parents` array is for all i2s clocks,
rename that to `apll_i2s_parents`.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-14-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:14 -07:00
AngeloGioacchino Del Regno
905b7430d3 clk: mediatek: mt8365: Convert simple_gate to mtk_gate clocks 
On this SoC some clocks apparently don't have different offsets for
set/clr/sta registers hence they can be set, cleared and status-read
on one register: this means that it was possible to use simpler gate
clocks instead of custom mtk_gate ones.

In preparation for converting this clock driver to the common probe
mechanism for MediaTek clocks, perform a conversion from simple_gate
to mtk_gate clocks since the latter does provide implicit support
for simple gate clocks as well.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-13-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:14 -07:00
AngeloGioacchino Del Regno
ab44c1a70e clk: mediatek: mt8365: Move apmixedsys clock driver to its own file 
In preparation for migrating all other mt8365 clocks to the common
mtk_clk_simple_probe(), move apmixedsys clocks to a different file.
While at it, use the builtin_platform_driver() macro for it.

During the conversion, error handling was added to the apmixedsys
probe function.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-12-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:14 -07:00
AngeloGioacchino Del Regno
274bc8561a clk: mediatek: mt2712: Change to use module_platform_driver macro 
Now that all of the clocks in clk-mt2712.c are using the common
mtk_clk_simple_{probe,remove}() callbacks we can safely migrate
to module_platform_driver.
While at it, also drop all references to `simple` in the specific
context of mt2712 as that was used in the past only to allow us
to have two platform_driver(s) in one file.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-11-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:14 -07:00
AngeloGioacchino Del Regno
c6368ce864 clk: mediatek: mt2712-apmixedsys: Add .remove() callback for module build 
Add a .remove() callback to the apmixedsys driver to allow full module
build; while at it, also change the usage of builtin_platform_driver()
to module_platform_driver() to actually make use of the new callback.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-10-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:13 -07:00
AngeloGioacchino Del Regno
ae567c3481 clk: mediatek: mt2712: Move apmixedsys clock driver to its own file 
The only clock driver that does not support mtk_clk_simple_probe() is
apmixedsys: in preparation for enabling module build of non-critical
mt2712 clocks, move this to its own file.
While at it, also fix some indentation issues in the PLLs table.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-9-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:13 -07:00
AngeloGioacchino Del Regno
20cace1b9d clk: mediatek: mt2712: Add error handling to clk_mt2712_apmixed_probe() 
This function was completely missing error handling: add it.

Fixes: e2f744a82d ("clk: mediatek: Add MT2712 clock support")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-8-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:13 -07:00
AngeloGioacchino Del Regno
f8c3e0e3f3 clk: mediatek: mt2712: Compress clock arrays entries to 90 columns 
Compress the clock arrays entries to allow a maximum of 90 columns:
this greatly increases readability and also generously reduces the
amount of lines.
While at it, also fix some indentation here and there.

This is a cosmetic change. No functional changes.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-7-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:13 -07:00
AngeloGioacchino Del Regno
67798a5bf2 clk: mediatek: mt2712: Migrate topckgen/mcucfg to mtk_clk_simple_probe() 
Now that the common mtk_clk_simple_{probe,remove}() functions can deal
with divider clocks it is possible to migrate more clock drivers to it:
in this case, it's about topckgen.
While at it, also perform a fast migration for mcucfg.

Thanks to the conversion, more error handling was added to the clocks
registration.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-6-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:13 -07:00
AngeloGioacchino Del Regno
1fe074b1f1 clk: mediatek: Add divider clocks to mtk_clk_simple_{probe,remove}() 
Add support for divider clocks register/unregister in the common
mtk_clk_simple_probe() and mtk_clk_simple_remove() functions.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-5-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:13 -07:00
AngeloGioacchino Del Regno
65c10c50c9 clk: mediatek: Migrate to mtk_clk_pdev_probe() for multimedia clocks 
Reduce duplication and simplify all MediaTek multimedia clock drivers
by migrating away from defining custom probe functions for each driver
and instead use mtk_clk_pdev_probe().

While at it, also add a .remove() callback to all of the multimedia
clock drivers where missing.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-4-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:13 -07:00
AngeloGioacchino Del Regno
2520912424 clk: mediatek: clk-mtk: Introduce clk_mtk_pdev_{probe,remove}() 
Introduce functions clk_mtk_pdev_probe() and clk_mtk_pdev_remove():
these will be useful to commonize the probe and remove handlers for
multimedia (clk-mtxxxx-mm) drivers as these are registered by the
mtk-mmsys driver instead of having their own devicetree compatible.

In order to do this, the main logic of clk_mtk_simple{probe,remove}()
was moved to new static __clk_mtk_simple_{probe,remove}() functions
that take as parameter a pointer to struct device_node because when
registering the clocks from mtk-mmsys we want to pass a pointer to
the clock driver's parent (which is, obviously, mtk-mmsys) struct
device_node instead.

As for the clock driver's platform data: for the devicetree case, we
keep using the standard match_data mechanism, else we retrieve it
from an id_table.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:13 -07:00
AngeloGioacchino Del Regno
4b476b0f45 clk: mediatek: clk-mtk: Switch to device_get_match_data() 
Instead of using of_device_get_match_data(), switch to the generic
device_get_match_data().

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Miles Chen <miles.chen@mediatek.com>
Tested-by: Chen-Yu Tsai <wenst@chromium.org>
Link: https://lore.kernel.org/r/20230306140543.1813621-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:50:13 -07:00
AngeloGioacchino Del Regno
da4a82dc67 clk: mediatek: mt8195: Add support for frequency hopping through FHCTL 
Add FHCTL parameters and register PLLs through FHCTL to add support
for frequency hopping and SSC. FHCTL will be enabled only on PLLs
specified in devicetree.

This commit brings functional changes only upon addition of
devicetree configuration.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230206100105.861720-8-angelogioacchino.delregno@collabora.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:46:45 -07:00
AngeloGioacchino Del Regno
4d586e10c4 clk: mediatek: mt8192: Add support for frequency hopping through FHCTL 
Add FHCTL parameters and register PLLs through FHCTL to add support
for frequency hopping and SSC. FHCTL will be enabled only on PLLs
specified in devicetree.

This commit brings functional changes only upon addition of
devicetree configuration.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230206100105.861720-7-angelogioacchino.delregno@collabora.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:46:41 -07:00
AngeloGioacchino Del Regno
45a5cbe05d clk: mediatek: mt8173: Add support for frequency hopping through FHCTL 
Add FHCTL parameters and register PLLs through FHCTL to add support
for frequency hopping and SSC. FHCTL will be enabled only on PLLs
specified in devicetree.

This commit brings functional changes only upon addition of
devicetree configuration.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230206100105.861720-6-angelogioacchino.delregno@collabora.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:46:38 -07:00
AngeloGioacchino Del Regno
f222a1baec clk: mediatek: mt6795: Add support for frequency hopping through FHCTL 
Add FHCTL parameters and register PLLs through FHCTL to add support
for frequency hopping and SSC. FHCTL will be enabled only on PLLs
specified in devicetree.

This commit brings functional changes only upon addition of
devicetree configuration.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230206100105.861720-5-angelogioacchino.delregno@collabora.com
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:46:35 -07:00
AngeloGioacchino Del Regno
4ba8590f62 dt-bindings: clock: mediatek,mt8186-fhctl: Support MT6795, MT8173/92/95 
MT6795, MT8173, MT8192 and MT8195 support Frequency Hopping: add the
compatibles for them.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20230206100105.861720-4-angelogioacchino.delregno@collabora.com
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
 2023-03-13 11:46:32 -07:00