Pull clk updates from Stephen Boyd:
"There's a bunch of patches here across drivers/clk/ to migrate drivers
to use struct clk_ops::determine_rate() instead of the round_rate()
one so that we can remove the round_rate clk_op entirely. Brian has
taken up that task which nobody else has wanted to do for close to a
decade. Thanks Brian!
This is all prerequisite work to get to the real task of improving the
clk rate setting process. Once we have determine_rate() used
everywhere, we'll be able to do things like chain the rate request
structs in linked lists to order the rate setting operations or add
more parameters without having to change every clk driver in
existence. It's also nice to not have multiple ways to do something
which just causes confusion for clk driver authors. Overall I'm glad
this is getting done.
Beyond this change we also have a tweak to the clk_lookup() function
in the core framework to use hashing on the clk name instead of a clk
tree walk with string comparisons. We _still_ rely on the clk name to
be unique, because historically we've used globally unique strings to
describe the clk tree topology. This tree walk becomes increasingly
slow as more clks are added to the system. Searching from the roots
for a duplicate is simple but pretty dumb and it wastes boot time so
we're using a hash table as an improvement. Ideally we wouldn't rely
on the strings to be unique at all, relegating them to simply debug
information, but that is future work that will likely require some
sort of Kconfig knob indicating strings aren't used for topology
description.
Outside of the core framework changes we have the usual new SoC
support and fixes to clk drivers for things that were discovered once
the clks were used by consumer drivers. Nothing in particular is
jumping out at me in the "misc" pile, except maybe the Amlogic driver
that has gone through a refactoring. That series got a fix from
testing in -next though so it seems likely that things have been
getting good test coverage for a couple weeks already"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (299 commits)
clk: microchip: core: remove duplicate roclk_determine_rate()
reset: aspeed: register AST2700 reset auxiliary bus device
dt-bindings: clock: ast2700: modify soc0/1 clock define
clk: tegra: do not overallocate memory for bpmp clocks
clk: ep93xx: Use int type to store negative error codes
clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driver
clk: loongson2: Add clock definitions for Loongson-2K0300 SoC
clk: loongson2: Avoid hardcoding firmware name of the reference clock
clk: loongson2: Allow zero divisors for dividers
clk: loongson2: Support scale clocks with an alternative mode
clk: loongson2: Allow specifying clock flags for gate clock
dt-bindings: clock: loongson2: Add Loongson-2K0300 compatible
clk: clocking-wizard: Fix output clock register offset for Versal platforms
clk: xilinx: Optimize divisor search in clk_wzrd_get_divisors_ver()
clk: mmp: pxa1908: Instantiate power driver through auxiliary bus
clk: s2mps11: add support for S2MPG10 PMIC clock
dt-bindings: clock: samsung,s2mps11: add s2mpg10
dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings
clk: stm32: introduce clocks for STM32MP21 platform
dt-bindings: stm32: add STM32MP21 clocks and reset bindings
...
* clk-determine-rate: (120 commits)
clk: microchip: core: remove duplicate roclk_determine_rate()
clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driver
clk: scmi: migrate round_rate() to determine_rate()
clk: ti: fapll: convert from round_rate() to determine_rate()
clk: ti: dra7-atl: convert from round_rate() to determine_rate()
clk: ti: divider: convert from round_rate() to determine_rate()
clk: ti: composite: convert from round_rate() to determine_rate()
clk: ti: dpll: convert from round_rate() to determine_rate()
clk: ti: dpll: change error return from ~0 to -EINVAL
clk: ti: dpll: remove round_rate() in favor of determine_rate()
clk: tegra: tegra210-emc: convert from round_rate() to determine_rate()
clk: tegra: super: convert from round_rate() to determine_rate()
clk: tegra: pll: convert from round_rate() to determine_rate()
clk: tegra: periph: divider: convert from round_rate() to determine_rate()
clk: tegra: divider: convert from round_rate() to determine_rate()
clk: tegra: audio-sync: convert from round_rate() to determine_rate()
clk: fixed-factor: drop round_rate() clk ops
clk: divider: remove round_rate() in favor of determine_rate()
clk: visconti: pll: convert from round_rate() to determine_rate()
clk: versatile: vexpress-osc: convert from round_rate() to determine_rate()
...
- Speed up clk_core_lookup() by using a hashtable
* clk-microchip:
ARM: at91: remove default values for PMC_PLL_ACR
clk: at91: add ACR in all PLL settings
clk: at91: sam9x7: Add peripheral clock id for pmecc
clk: at91: clk-master: Add check for divide by 3
clk: at91: clk-sam9x60-pll: force write to PLL_UPDT register
ARM: at91: pm: save and restore ACR during PLL disable/enable
* clk-lookup:
clk: Use hashtable for global clk lookups
clk: Sort include statements
* clk-st:
dt-bindings: stm32: cosmetic fixes for STM32MP25 clock and reset bindings
clk: stm32: introduce clocks for STM32MP21 platform
dt-bindings: stm32: add STM32MP21 clocks and reset bindings
Pull more RISC-V updates from Paul Walmsley:
- Support for the RISC-V-standardized RPMI interface.
RPMI is a platform management communication mechanism between OSes
running on application processors, and a remote platform management
processor. Similar to ARM SCMI, TI SCI, etc. This includes irqchip,
mailbox, and clk changes.
- Support for the RISC-V-standardized MPXY SBI extension.
MPXY is a RISC-V-specific standard implementing a shared memory
mailbox between S-mode operating systems (e.g., Linux) and M-mode
firmware (e.g., OpenSBI). It is part of this PR since one of its use
cases is to enable M-mode firmware to act as a single RPMI client for
all RPMI activity on a core (including S-mode RPMI activity).
Includes a mailbox driver.
- Some ACPI-related updates to enable the use of RPMI and MPXY.
- The addition of Linux-wide memcpy_{from,to}_le32() static inline
functions, for RPMI use.
- An ACPI Kconfig change to enable boot logos on any ACPI-using
architecture (including RISC-V)
- A RISC-V defconfig change to add GPIO keyboard and event device
support, for front panel shutdown or reboot buttons
* tag 'riscv-for-linus-6.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (26 commits)
clk: COMMON_CLK_RPMI should depend on RISCV
ACPI: support BGRT table on RISC-V
MAINTAINERS: Add entry for RISC-V RPMI and MPXY drivers
RISC-V: Enable GPIO keyboard and event device in RV64 defconfig
irqchip/riscv-rpmi-sysmsi: Add ACPI support
mailbox/riscv-sbi-mpxy: Add ACPI support
irqchip/irq-riscv-imsic-early: Export imsic_acpi_get_fwnode()
ACPI: RISC-V: Add RPMI System MSI to GSI mapping
ACPI: RISC-V: Add support to update gsi range
ACPI: RISC-V: Create interrupt controller list in sorted order
ACPI: scan: Update honor list for RPMI System MSI
ACPI: Add support for nargs_prop in acpi_fwnode_get_reference_args()
ACPI: property: Refactor acpi_fwnode_get_reference_args() to support nargs_prop
irqchip: Add driver for the RPMI system MSI service group
dt-bindings: Add RPMI system MSI interrupt controller bindings
dt-bindings: Add RPMI system MSI message proxy bindings
clk: Add clock driver for the RISC-V RPMI clock service group
dt-bindings: clock: Add RPMI clock service controller bindings
dt-bindings: clock: Add RPMI clock service message proxy bindings
mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driver
...
The RISC-V platform management interface (RPMI) is only available on
RISC-V platforms. Hence add a dependency on RISCV, to prevent asking
the user about this driver when configuring a kernel for a different
architecture.
Fixes: 5ba9f520f4 ("clk: Add clock driver for the RISC-V RPMI clock service group")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Paul Walmsley <pjw@kernel.org>
Pull SoC driver updates from Arnd Bergmann:
"Lots of platform specific updates for Qualcomm SoCs, including a new
TEE subsystem driver for the Qualcomm QTEE firmware interface.
Added support for the Apple A11 SoC in drivers that are shared with
the M1/M2 series, among more updates for those.
Smaller platform specific driver updates for Renesas, ASpeed,
Broadcom, Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale
SoCs.
Driver updates in the cache controller, memory controller and reset
controller subsystems.
SCMI firmware updates to add more features and improve robustness.
This includes support for having multiple SCMI providers in a single
system.
TEE subsystem support for protected DMA-bufs, allowing hardware to
access memory areas that managed by the kernel but remain inaccessible
from the CPU in EL1/EL0"
* tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (139 commits)
soc/fsl/qbman: Use for_each_online_cpu() instead of for_each_cpu()
soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver
soc: fsl: qe: Change GPIO driver to a proper platform driver
tee: fix register_shm_helper()
pmdomain: apple: Add "apple,t8103-pmgr-pwrstate"
dt-bindings: spmi: Add Apple A11 and T2 compatible
serial: qcom-geni: Load UART qup Firmware from linux side
spi: geni-qcom: Load spi qup Firmware from linux side
i2c: qcom-geni: Load i2c qup Firmware from linux side
soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem
soc: qcom: geni-se: Cleanup register defines and update copyright
dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus
Documentation: tee: Add Qualcomm TEE driver
tee: qcom: enable TEE_IOC_SHM_ALLOC ioctl
tee: qcom: add primordial object
tee: add Qualcomm TEE driver
tee: increase TEE_MAX_ARG_SIZE to 4096
tee: add TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF
tee: add TEE_IOCTL_PARAM_ATTR_TYPE_UBUF
tee: add close_context to TEE driver operation
...
Pull SoC dt updates from Arnd Bergmann:
"There are five sets of new SoCs that get added in existing families,
all of them being either upgrades or cut-down versions of the older
chips:
- Apple M2 Pro, M2 Max and M2 Ultra, used in the 2022/2023 generation
of high-end workstations and laptops from Apple. Linux has been
working on these for a while but stil requires patches.
- Axis Artpec8 is an Armv8 chip based on Samsung Exynos design,
unlike the earlier Armv7 Artpec6 from the same company that was
part of a separate family of chips.
- NXP i.MX91 is a cut-down version of i.MX93, using only a single
Cortex-A55 core.
- Qualcomm Lemans Auto is a variant of the Lemans SoC that was
originally merged under the sa8775p name, the differences being
mostly the firmware configuration of the platform.
- Four new Renesas SoCs RZ/T2H (r9a09g077m44), RZ/N2H (r9a09g087m44),
RZ/T2H (r9a09g077), and RZ/N2H (r9a09g087) are all industrial
bedded SoCs based on Cortex-A55 cores
In total, there are 65 new machines, including:
- Industrial embedded system and single-board computers based on NXP,
Allwinner, TI, Rockchips, Marvell, Xilinx Spacemit, Starfive chips.
- Reference boards for the newly added Renesas, Qualcomm, NXP and
Axis ARMv8 chips as well as Microchip's MPFS RISC-V SoC
- Laptops and Workstations using Apple M2 and Qualcomm Snapdragon X1
chips.
- Several Samsung phones using Qualcomm Snapdragon chips
- Set-top boxes based on Allwinner H313
- Five BMC boards using 32-bit ASpeed SoCs
- Three network routers using IXP4xx (ARMv5!) and Broadcom bcm4708
(ARMv7) SoCs
Two machines get phased out because they were available only in small
quantities but never made it into products: one STi407 based reference
board, and a Snapdragon 845 based Chromebook.
Aside from the newly added machines, a lot of work went into improving
hardware support on the existing machines and cleaning up contents for
validation"
* tag 'soc-dt-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (931 commits)
arm64: dts: apm-shadowcat: Drop "apm,xgene2-pcie" compatible
arm64: dts: apm-shadowcat: Move slimpro nodes out of "simple-bus" node
ARM: dts: microchip: sam9x7: Add qspi controller
arm64: dts: qcom: Add MST pixel streams for displayport
arm64: dts: qcom: sm6350: correct DP compatibility strings
arm64: dts: qcom: monaco-evk: Enable Adreno 623 GPU
arm64: dts: qcom: qcs8300-ride: Enable Adreno 623 GPU
arm64: dts: qcom: qcs8300: Add gpu and gmu nodes
arm64: dts: allwinner: h313: Add Amediatech X96Q
dt-bindings: arm: sunxi: Add Amediatech X96Q
arm64: dts: apple: t8015: Add SPMI node
arm64: dts: apple: t8012: Add SPMI node
arm64: dts: apple: Add J180d (Mac Pro, M2 Ultra, 2023) device tree
arm64: dts: rockchip: Add devicetree for the ROC-RK3588-RT
dt-bindings: arm: rockchip: Add Firefly ROC-RK3588-RT
arm64: dts: rockchip: update pinctrl names for Radxa E52C
arm64: dts: rockchip: remove vcc_3v3_pmu regulator for Radxa E52C
arm64: dts: apple: Add J474s, J475c and J475d device trees
arm64: dts: apple: Add J414 and J416 Macbook Pro device trees
arm64: dts: apple: Add initial t6020/t6021/t6022 DTs
...
The sp7021 clock driver has its own shifted high word mask macro,
similar to the ones many Rockchip drivers have.
Remove it, and replace instances of it with hw_bitfield.h's
FIELD_PREP_WM16 macro, which does the same thing except in a common
macro that also does compile-time error checking.
This was compile-tested with 32-bit ARM with Clang, no runtime tests
were performed as I lack the hardware. However, I verified that fix
commit 5c667d5a5a ("clk: sp7021: Adjust width of _m in HWM_FIELD_PREP()")
is not regressed. No warning is produced.
Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Yury Norov (NVIDIA) <yury.norov@gmail.com>
struct tegra_bpmp::clocks is a pointer to a dynamically allocated array
of pointers to 'struct tegra_bpmp_clk'.
But the size of the allocated area is calculated like it is an array
containing actual 'struct tegra_bpmp_clk' objects - it's not true, there
are just pointers.
Found by Linux Verification Center (linuxtesting.org) with Svace static
analysis tool.
Fixes: 2db12b15c6 ("clk: tegra: Register clocks from root to leaf")
Signed-off-by: Fedor Pchelkin <pchelkin@ispras.ru>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Change the 'ret' variable in ep93xx_uart_clock_init() from unsigned int to
int, as it needs to store either negative error codes or zero.
Storing the negative error codes in unsigned type, doesn't cause an issue
at runtime but can be confusing. Additionally, assigning negative error
codes to unsigned type may trigger a GCC warning when the -Wsign-conversion
flag is enabled.
No effect on runtime.
Signed-off-by: Qianfeng Rong <rongqianfeng@vivo.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The conditional check for the PLL0 multiplier 'm' used a logical AND
instead of OR, making the range check ineffective. This patch replaces
&& with || to correctly reject invalid values of 'm' that are either
less than or equal to 0 or greater than LPC18XX_PLL0_MSEL_MAX.
This ensures proper bounds checking during clk rate setting and rounding.
Fixes: b04e0b8fd5 ("clk: add lpc18xx cgu clk driver")
Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com>
[sboyd@kernel.org: 'm' is unsigned so remove < condition]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The clock controller of Loongson-2K0300 consists of three PLLs, requires
an 120MHz external reference clock to function, and generates clocks in
various frequencies for SoC peripherals.
Clock definitions for previous SoC generations could be reused for most
clock hardwares. There're two gates marked as critical, clk_node_gate
and clk_boot_gate, which supply the CPU cores and the system
configuration bus. Disabling them leads to a SoC hang.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Loongson-2K0300 requires a reference clock with a frequency different
from previous SoCs (120MHz v.s. 100MHz), thus hardcoding the firmware
name of the reference clock as ref_100m isn't a good idea.
This patch retrives the clock name of the reference clock dynamically
during probe, avoiding the hardcoded pdata structure and preparing for
support of future SoCs.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
LS2K0300 and LS2K0500 ship divider clocks which allows zero divisors,
in which case the divider acts the same as one is specified.
Let's pass CLK_DIVIDER_ALLOW_ZERO when registering divider clocks to
prepare for future introduction of these clocks.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
LS2K0300 and LS2K1500 ship scale clocks with an alternative mode.
There's one mode bit in clock configuration register indicating the
operation mode.
When mode bit is unset, the scale clock acts the same as previous
generation of scale clocks. When it's set, a different equation for
calculating result frequency, Fout = Fin / (scale + 1), is used.
This patch adds frequency calculation support for the scale clock
variant. A helper macro, CLK_SCALE_MODE, is added to simplify
definitions.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Some gate clocks need to be supplied with flags, e.g., it may be
required to specify CLK_IS_CRTICAL for CPU clocks.
Add a field to loongson2_clk_board_info for representing clock flags,
and specify it when registering gate clocks. A new helper macro,
CLK_GATE_FLAGS, is added to simplify definitions.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The output clock register offset used in clk_wzrd_register_output_clocks
was incorrectly referencing 0x3C instead of 0x38, which caused
misconfiguration of output dividers on Versal platforms.
Correcting the off-by-one error ensures proper configuration of output
clocks.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Optimise the clock wizard divisor calculation by eliminating the innermost
loop over output divider o. Earlier there was an error that is returned
if the WZRD_MIN_ERR is not achieved error is returned now it computes
the best possible frequency.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The power domain driver shares the APMU clock controller's registers.
Instantiate the power domain driver through the APMU clock driver using
the auxiliary bus.
Also create a separate Kconfig entry for the PXA1908 clock driver to
allow (de)selecting the driver at will and selecting
CONFIG_AUXILIARY_BUS.
Signed-off-by: Duje Mihanović <duje@dujemihanovic.xyz>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for Samsung's S2MPG10 PMIC clock, which is similar to the
existing PMIC clocks supported by this driver.
S2MPG10 has three clock outputs @ 32kHz: AP, peri1 and peri2.
Acked-by: Stephen Boyd <sboyd@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
A clk lookup using clk_core_lookup() is currently somewhat expensive
since it has to walk the whole clk tree to find a match. This is
extremely bad in the clk_core_init() function where it is used to look
for clk name conflicts, which is always the worst case of walking the
whole tree. Moreover, the number of clks checked increases as more
clks are registered, causing each subsequent clk registration becoming
slower.
Add a hashtable for doing clk lookups to replace the tree walk method.
On arm64 this increases kernel memory usage by 4 KB for the hashtable,
and 16 bytes (2 pointers) for |struct hlist_node| in each clk. On a
platform with around 800 clks, this reduces the time spent in
clk_core_lookup() significantly:
| PID 0 | kworker |
| before | after | before | after |
-------------------------------------------
avg | 203 us | 2.7 us | 123 us | 1.5 us |
-------------------------------------------
min | 4.7 us | 2.3 us | 102 us | 0.9 us |
-------------------------------------------
max | 867 us | 4.8 us | 237 us | 3.5 us |
-------------------------------------------
culm | 109 ms | 1.5 ms | 21 ms | 0.3 ms |
This in turn reduces the time spent in clk_hw_register(), and
ultimately, boot time. On a different system with close to 700 clks,
This reduces boot time by around 110 ms. While this doesn't seem like
a lot, this helps in cases where minimizing boot time is important.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Tested-by: Brian Masney <bmasney@redhat.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
The clk core has its include statements in some random order.
Clean it up before we add more.
Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for the MT8196 ovl1 clock controller, which provides clock
gate control for the display system. It is integrated with the mtk-mmsys
driver, which registers the ovl1 clock driver via
platform_device_register_data().
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for the MT8196 ovl0 clock controller, which provides clock
gate control for the display system. It is integrated with the mtk-mmsys
driver, which registers the ovl0 clock driver via
platform_device_register_data().
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for the MT8196 disp-ao clock controller, which provides
clock gate control for the display system. It is integrated with the
mtk-mmsys driver, which registers the disp-ao clock driver via
platform_device_register_data().
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for the MT8196 disp1 clock controller, which provides clock
gate control for the display system. It is integrated with the mtk-mmsys
driver, which registers the disp1 clock driver via
platform_device_register_data().
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org> # CLK_OPS_PARENT_ENABLE removal
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Add support for the MT8196 disp0 clock controller, which provides clock
gate control for the display system. It is integrated with the mtk-mmsys
driver, which registers the disp0 clock driver via
platform_device_register_data().
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Laura Nao <laura.nao@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
